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WIZ610MJ

WIZ610MJ

The WIZ610MJ is a compact Ethernet module that integrates the W6100 hardwired TCP/IP chip with an embedded PHY and an RJ45 MAG-JACK. It supports both IPv4 and IPv6 Dual Stack, enabling flexible networking for modern embedded systems. By combining all essential Ethernet hardware in one module, it eliminates complex PCB design for the transformer and RJ45 interface. The WIZ610MJ is ideal for developers who want to implement network-enabled systems quickly and reliably.

Pin Information​

P1​

PinTypeNameDescription
1PGNDGround
2PGNDGround
3P3V3D3.3 V Power
4IMODESPI/BUS Select pin
SPI : Low
BUS : High
5ISCSnSPI Chip select (active low)
6ISCLKSPI Clock input
7IMOSI/A0SPI : Master-Out / Slave-In
BUS : A0
8O/IMISO/A1SPI : Master-In / Slave-Out
BUS : A1
9IRDnRead Strobe
SPI : indicates Read Operation
BUS : indicates Read Operation
10IWRnWrite Strobe
SPI : indicates Read Operation
BUS : indicates Write Operation

P2​

PinTypeNameDescription
1IRSTnHardware reset (active low, ≥ 1 µs)
2OINTnInterrupt output (low-active)
3IOD7Data Bus pin SPI : DAT [7:0] must be floated.
BUS : Data is carried over DAT [7:0] between HOST and W6100
4IOD6Data Bus pin SPI : DAT [7:0] must be floated.
BUS : Data is carried over DAT [7:0] between HOST and W6100
5IOD5Data Bus pin SPI : DAT [7:0] must be floated.
BUS : Data is carried over DAT [7:0] between HOST and W6100
6IOD4Data Bus pin SPI : DAT [7:0] must be floated.
BUS : Data is carried over DAT [7:0] between HOST and W6100
7IOD3Data Bus pin SPI : DAT [7:0] must be floated.
BUS : Data is carried over DAT [7:0] between HOST and W6100
8IOD2Data Bus pin SPI : DAT [7:0] must be floated.
BUS : Data is carried over DAT [7:0] between HOST and W6100
9IOD1Data Bus pin SPI : DAT [7:0] must be floated.
BUS : Data is carried over DAT [7:0] between HOST and W6100
10IOD0Data Bus pin SPI : DAT [7:0] must be floated.
BUS : Data is carried over DAT [7:0] between HOST and W6100

Features​

  • Supports IPv4/IPv6 Dual Stack
  • Hardwired Internet protocols: TCP, UDP, ICMPv6, ICMPv4, IGMP, MLDv1, ARP, PPPoE
  • 8 independent sockets with 32 KB internal TX/RX buffer
  • SOCKET-less commands for ARP, PING, and ICMPv6 (DAD, NA, RS)
  • High-speed SPI interface (Mode 0/3)
  • Parallel bus mode with 8-bit data and 2 address lines
  • Auto-negotiation and Auto-MDIX (for 10/100 Mbps)
  • Ethernet Power-down & Main Clock Switching for low-power operation
  • Supports Wake-on-LAN (UDP)
  • 3.3 V operation with 5 V I/O tolerance
  • 2 × 10-pin headers (2.54 mm pitch)
  • Operating temperature: −40 °C to +85 °C

Electrical Characteristics​

SymbolParameterPinsMinTypMaxUnit
VDDSupply voltage3.3 V2.973.33.63V
VIHHigh-level inputALL2.0–-V
VILLow-level inputALL––0.8V
VOHHigh-level outputALL2.43.3–V
VOLLow-level outputALL0.0–0.4V
IDDSupply current (Normal)3.3 V–132–mA
IPDSupply current (Power-down)3.3 V–13–mA

Documentation​

TitleDescriptionLink
DatasheetTechnical datasheet for WIZ610MJ moduledownload WIZ610MJ Datasheet v1.0

Software Resources​

Driver

ResourceDescription
ioLibrary_DriverOfficial WIZnet driver library supporting W6100 and other Ethernet controllers

Note: The ioLibrary_Driver provides MCU-independent implementations of TCP/IP services for WIZnet chips.
Includes DHCP, DNS, SNTP, MQTT, TFTP, and HTTP server modules.

Hardware Resources​

TitleRevisionDescriptionDownloadNotes
schematic1.0Circuit diagram for hardware design referencedownload Altium
download PDF		—
3D File1.03D model for mechanical design and visualizationdownload STEP—
Part list1.0List of components used in the hardwaredownload PDF—

Mechanical Information​

  • Form factor: Compact ioModule with integrated RJ45 MAG-JACK
  • Pin pitch: 2.54 mm (2 × 10 header)
  • Dimensions: 28.0 × 28.0 mm (typ.)
ProductDescription
W6100 ChipStand-alone W6100 Ethernet controller (IPv4/IPv6 Dual Stack)
W610ioCompact SPI Ethernet module using W6100 chip
W5500-ioSPI Ethernet