W7500P
W7500P

The IOP4IoT W7500P chip is the one-chip solution which integrates an ARM Cortex-M0, 128KB Flash, hardwired TCP/IP core for various embedded application platform, 10/100 Ethernet MAC and PHY, and especially internet of things. The TCP/IP core is a market-proven hardwired TCP/IP stack and PHY is IC plus IP101G, an IEEE 802.3/802.3u Fast Ethernet Transcevier for 10/100Mbps. The Hardwired TCP/IP stack supports the TCP, UDP, IPv4, ICMP, ARP, IGMP and PPPoE which has been used in various applications for more than 15 years. W7500P suits users who need Internet connectivity best.
Details
Block Diagram
TBDPin Map

Features
- ARM Cortex-M0( MAX 48MHz)
- Hardwired TCP/IP Core
- 8 Sockets
- SRAM for socket: 32 KB
- PHY : IC+(IP101G)
- Memories
- Flas: 128 KB, SRAM: 16KB, ROM for boot code: 6 KB
- Clock, reset and supply management
- POR (Power-On Reset)
- Internal Voltage Regulator : 3.3V to 1.5V
- 8-to-24MHz external crystal oscillator
- Internal 8MHz RC Oscillator
- PLL for CPU clock
- ADC : 12bit, 8ch, 1Msps
- DMA
- 6-channel DMA controller(Peripheral supported: UARTs, SPIs)
- GPIO
- 34 I/Os (15 IO x 2ea, 4 IO x 1ea)
- Debug mode
- Serial Wire Debug (SWD)
- Timer/PWM
- 1 Watchdog (32-bit down-counter)
- 4 Timers (32-bit or 16-bit down-counter)
- 8 PWMs (32-bit counter/timers with programmable 6-bit prescaler)
- Communication Interfaces
- 3 UART (2 UARTs with FIFO and Flow Control, 1 simple UART)
- 2 SPI
- Crypto
- 1 RNG (Random Number Generator): 32-bit random number
- Package
- 64 LQFP (7x7 mm)
Documentation
Datasheet
Title | Description | Notes |
---|---|---|
Technical specifications and features of the W7500P chip | - | |
How to control the internal PHY of W7500P using indirect register access via PHYR/PHYSR, with busy flag polling for read/write operations. | - |
Technical Documents
Title | Description | Notes |
---|---|---|
Known issues, register details, and functional corrections for the W7500P chip | - | |
Known issues and corrections for the chips | - | |
W7500x PHY is accessed indirectly via PHYR/PHYSR registers; read/write operations use busy flag polling to ensure proper completion | - | |
Technical specifications and features of the W7500P chip | - |
Getting Started
Title | Description | Notes |
---|---|---|
Step-by-step guide for installing KEIL development environment for W7500P | - | |
Tutorial for creating new KEIL projects for W7500P development | - | |
Guide for using MDK with W7500P peripheral examples | - | |
Instructions for using GCC compiler with W7500P peripheral examples | - | |
Guide for using In-System Programming tool with W7500P | - |
Software Resources
- Driver
Driver
Resource | Description |
---|---|
The W7500p Standard Peripherals library provides a rich set of examples covering the main features of each peripheral |
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Hardware Resources
Technical Resources
Resource | Description | Notes |
---|---|---|
Typical application schemati | Includes recommended circuit design |
Test & Certification
Resource | Description | Notes |
---|---|---|
[ | Confirmation of ESD Test | - |
[ | Results and documentation of Ethernet standard compliance tests | Covers IEEE 802.3 physical and protocol layer verification |
[ | Cable length performance test results | Verified up to 100m Ethernet cable |
[ | Electromagnetic compatibility test reports | Covers conducted and radiated emissions |
[ | Reliability and endurance test reports | Includes thermal cycling and aging analysis |
[ | Official certification documents | CE, FCC, and RoHS certificates available |
Related modules
- Evaluation Boards
- Serial to Ethernet module