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WIZ750SR-T1L Datasheet

Hardware Specification

Product Spec Table

CategoryDescription
MCUARM Cortex-M0 CoreW7500
48Mhz maximum frequency
Internal 8Mhz RC Oscillator
Flash: 128KB
Large flexible-size SRAM buffer for various User Application
- Min 16KB available if full 32KB socket buffer used
- Max 48KB available if no socket buffer used
ROM for boot code: 6 KB
Hardwired TCP/IP Core8 independent Sockets
SRAM for socket: 32KB
MII (Medium-Independent Interface)
TCP/IP Protocols: TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE
PHYTransceiver10Base-T1L Ethernet PHY
SerialSignalTXD, RXD, RTS, CTS, GND
ParametersParity: None, Odd, Even
Data bits: 7, 8 bit
Flow control: None, RTS / CTS, XON / XOFF
SpeedUp to 230Kbps
Dimension100mm x 50mm x 1.6mm
Connector type2.54mm Pitch 6x2 Pin-header(Data Line), 3.81mm Pitch 3pin Pluggable terminal Block(Jack)
Input VoltagePower - 5.0V ~ 36.0V
Data Line - 3.3V LVTTL
Temperature-40℃ ~ 85℃ (Operation, Storage range)

WIZ750SR-T1L Callout


WIZ750SR-T1L Indicator

PartsDescription
LD1Link LED
LD2TCP Connection LED
LD3Power LED
LD4Application Running LED
LD5User Config LED
LD6User Config LED

WIZ750SR-T1L Block Diagram


Schematic & Artwork

H/W versionTypeFiletypeDownload LinkRemarks
1.0-Altium Download-
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3D File

H/W versionTypeFiletypeDownload LinkRemarks
1.0-STEP Download-

Part list

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Electrical Characteristics

SymbolParameterPinsMinTypMaxUnit
PowerPower SourceDC JACK5.0-36V
VCCW7500 Operating VoltageW7500 VCC3.1353.33.465V
VssGroundALL050mV
fFCLKInternal CPU clock frequencyW75000-48MHz
VIOI/O Signal voltage (Tolerance)W7500 IOVss-0.33.33.6V

Operating Conditions

SymbolParameterPinsMinTypMaxUnit
TstgStorage Temperature (max)ALL-4085
TAAmbient operating temperatureALL-4085

Connector Specification

Power Source Select Pin (J1, J9)

PartsPin NumberSignalDescription
J113V3_OUTThis pin is connect with IC1(Step Down Convertor) output
:::23V3System Power (3.3V)
PartsPin NumberSignalDescription
J91DC_JACKThis pin is connect with DC_Jack
:::2VCCThis pin is connect with J11_VCC pin
:::33V3System Power (3.3V)

Set J1 and J9 according to the way you want to supply power to the module.

Power SourceInput VoltageJ1 SetJ9 Set
DC Jack5 - 36 VDC1, 2 pin ShortNC
J11_VCC pin3.3 VDCNC2, 3 pin Short
J11_VCC pin5 - 36 VDC1, 2 pin Short1, 2 pin Short

APP/BOOT Pin (J7, J8)

PartsPin NumberSignalDescription
J71APP BOOTApplication Jump at BOOT mode (Active Low)
When this pin is held Low and reset, the system runs only the Boot code and does not jump to the App code, unlike normal operation.
This mode is used for debugging and forced uploading to the App area.
:::2GNDSystem Ground
PartsPin NumberSignalDescription
J81BOOTBoot mode Pin (Active High)
:::2VCCSystem Power (3.3V)

For pin J7, the Boot mode refers to the code area’s Boot process. For pin J8, the Boot mode refers to the W7500’s native Boot mode, which allows ISP (In-System Programming) functionality.


SWD(JTAG) Pin (J10)

PartsPin NumberSignalDescription
J101VCCSystem Power (3.3V)
:::2SWDIOSWD(JTAG) Data I/O pin
:::3SWCLKSWD(JTAG) Clock pin
:::4nRESETSystem Reset signal (Active Low)
:::5GNDSystem Ground

ISP/DEBUG Port (J6)

PartsPin NumberSignalDescription
J61VCCSystem Power (3.3V)
:::2BOOTBoot mode Pin (Active High)
:::3UART2 TXISP Serial TX
:::4UART2 RXISP Serial RX
:::5nRESETSystem Reset signal (Active Low)
:::6GNDSystem Ground

Serial Port (J11)

PartsPin NumberSignalDescription
J111nRESETSystem Reset signal (Active Low)
:::2VCCSystem Power (3.3V)
:::3UART0 RXData Serial RX
:::4VCCSystem Power (3.3V)
:::5UART0 CTSData Serial CTS
:::6FACTORY RESETFactory Reset signal (Active 5.0s Low)
:::7UART0 TXData Serial TX
:::8HW_TRIG/UART0 DSR/ TCPHW Trigger/ Data Serial DSR / TCP Status
:::9UART0 RTSData Serial RTS
:::10UART0 DTR/PHY LINKData Serial DTR / Phy link
:::11GNDSystem Ground
:::12GNDSystem Ground

SPE Terminal Block (J2)

PartsPin NumberSignalDescription
J21PPositive (+) line of the SPE differential pair
:::2NNegative (–) line of the SPE differential pair
:::3EarthEarth Ground

Dimension