49 #define _W5500_SPI_READ_ (0x00 << 2) //< SPI interface Read operation in Control Phase
50 #define _W5500_SPI_WRITE_ (0x01 << 2) //< SPI interface Write operation in Control Phase
52 #define WIZCHIP_CREG_BLOCK 0x00 //< Common register block
53 #define WIZCHIP_SREG_BLOCK(N) (1+4*N) //< Socket N register block
54 #define WIZCHIP_TXBUF_BLOCK(N) (2+4*N) //< Socket N Tx buffer address block
55 #define WIZCHIP_RXBUF_BLOCK(N) (3+4*N) //< Socket N Rx buffer address block
57 #define WIZCHIP_OFFSET_INC(ADDR, N) (ADDR + (N<<8)) //< Increase offset address
111 #define MR (_WIZCHIP_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_CREG_BLOCK << 3))
117 #define GAR (_WIZCHIP_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_CREG_BLOCK << 3))
123 #define SUBR (_WIZCHIP_IO_BASE_ + (0x0005 << 8) + (WIZCHIP_CREG_BLOCK << 3))
129 #define SHAR (_WIZCHIP_IO_BASE_ + (0x0009 << 8) + (WIZCHIP_CREG_BLOCK << 3))
135 #define SIPR (_WIZCHIP_IO_BASE_ + (0x000F << 8) + (WIZCHIP_CREG_BLOCK << 3))
141 #define INTLEVEL (_WIZCHIP_IO_BASE_ + (0x0013 << 8) + (WIZCHIP_CREG_BLOCK << 3))
157 #define IR (_WIZCHIP_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_CREG_BLOCK << 3))
174 #define IMR (_WIZCHIP_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_CREG_BLOCK << 3))
181 #define SIR (_WIZCHIP_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_CREG_BLOCK << 3))
189 #define SIMR (_WIZCHIP_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_CREG_BLOCK << 3))
198 #define RTR (_WIZCHIP_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_CREG_BLOCK << 3))
205 #define RCR (_WIZCHIP_IO_BASE_ + (0x001B << 8) + (WIZCHIP_CREG_BLOCK << 3))
211 #define PTIMER (_WIZCHIP_IO_BASE_ + (0x001C << 8) + (WIZCHIP_CREG_BLOCK << 3))
217 #define PMAGIC (_WIZCHIP_IO_BASE_ + (0x001D << 8) + (WIZCHIP_CREG_BLOCK << 3))
223 #define PHAR (_WIZCHIP_IO_BASE_ + (0x001E << 8) + (WIZCHIP_CREG_BLOCK << 3))
229 #define PSID (_WIZCHIP_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_CREG_BLOCK << 3))
235 #define PMRU (_WIZCHIP_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_CREG_BLOCK << 3))
243 #define UIPR (_WIZCHIP_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_CREG_BLOCK << 3))
251 #define UPORTR (_WIZCHIP_IO_BASE_ + (0x002C << 8) + (WIZCHIP_CREG_BLOCK << 3))
257 #define PHYCFGR (_WIZCHIP_IO_BASE_ + (0x002E << 8) + (WIZCHIP_CREG_BLOCK << 3))
273 #define VERSIONR (_WIZCHIP_IO_BASE_ + (0x0039 << 8) + (WIZCHIP_CREG_BLOCK << 3))
307 #define Sn_MR(N) (_WIZCHIP_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
325 #define Sn_CR(N) (_WIZCHIP_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
342 #define Sn_IR(N) (_WIZCHIP_IO_BASE_ + (0x0002 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
364 #define Sn_SR(N) (_WIZCHIP_IO_BASE_ + (0x0003 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
371 #define Sn_PORT(N) (_WIZCHIP_IO_BASE_ + (0x0004 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
378 #define Sn_DHAR(N) (_WIZCHIP_IO_BASE_ + (0x0006 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
387 #define Sn_DIPR(N) (_WIZCHIP_IO_BASE_ + (0x000C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
396 #define Sn_DPORT(N) (_WIZCHIP_IO_BASE_ + (0x0010 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
402 #define Sn_MSSR(N) (_WIZCHIP_IO_BASE_ + (0x0012 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
410 #define Sn_TOS(N) (_WIZCHIP_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
417 #define Sn_TTL(N) (_WIZCHIP_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
435 #define Sn_RXBUF_SIZE(N) (_WIZCHIP_IO_BASE_ + (0x001E << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
445 #define Sn_TXBUF_SIZE(N) (_WIZCHIP_IO_BASE_ + (0x001F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
455 #define Sn_TX_FSR(N) (_WIZCHIP_IO_BASE_ + (0x0020 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
466 #define Sn_TX_RD(N) (_WIZCHIP_IO_BASE_ + (0x0022 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
479 #define Sn_TX_WR(N) (_WIZCHIP_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
487 #define Sn_RX_RSR(N) (_WIZCHIP_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
499 #define Sn_RX_RD(N) (_WIZCHIP_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
507 #define Sn_RX_WR(N) (_WIZCHIP_IO_BASE_ + (0x002A << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
516 #define Sn_IMR(N) (_WIZCHIP_IO_BASE_ + (0x002C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
522 #define Sn_FRAG(N) (_WIZCHIP_IO_BASE_ + (0x002D << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
534 #define Sn_KPALVTR(N) (_WIZCHIP_IO_BASE_ + (0x002F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
569 #define MR_PPPOE 0x08
583 #define IR_CONFLICT 0x80
589 #define IR_UNREACH 0x40
594 #define IR_PPPoE 0x20
603 #define PHYCFGR_RST ~(1<<7) //< For PHY reset, must operate AND mask.
604 #define PHYCFGR_OPMD (1<<6) // Configre PHY with OPMDC value
605 #define PHYCFGR_OPMDC_ALLA (7<<3)
606 #define PHYCFGR_OPMDC_PDOWN (6<<3)
607 #define PHYCFGR_OPMDC_NA (5<<3)
608 #define PHYCFGR_OPMDC_100FA (4<<3)
609 #define PHYCFGR_OPMDC_100F (3<<3)
610 #define PHYCFGR_OPMDC_100H (2<<3)
611 #define PHYCFGR_OPMDC_10F (1<<3)
612 #define PHYCFGR_OPMDC_10H (0<<3)
613 #define PHYCFGR_DPX (1<<2)
614 #define PHYCFGR_SPD (1<<1)
615 #define PHYCFGR_LNK (1<<0);
617 #define PHYCFGR_DPX_FULL 1
618 #define PHYCFGR_DPX_HALF 0
619 #define PHYCFGR_SPD_100 1
620 #define PHYCFGR_SDP_10 0
621 #define PHYCFGR_LNK_ON 1
622 #define PHYCFGR_LNK_OFF 0
659 #define Sn_MR_MULTI 0x80
667 #define Sn_MR_BCASTB 0x40
676 #define Sn_MR_ND 0x20
683 #define Sn_MR_UCASTB 0x10
689 #define Sn_MR_MACRAW 0x04
695 #define Sn_MR_UDP 0x02
700 #define Sn_MR_TCP 0x01
705 #define Sn_MR_CLOSE 0x00
718 #define Sn_MR_MFEN Sn_MR_MULTI
726 #define Sn_MR_MMB Sn_MR_ND
733 #define Sn_MR_MIP6B Sn_MR_UCASTB
742 #define Sn_MR_MC Sn_MR_ND
748 #define SOCK_STREAM Sn_MR_TCP
752 #define SOCK_DGRAM Sn_MR_UDP
768 #define Sn_CR_OPEN 0x01
778 #define Sn_CR_LISTEN 0x02
789 #define Sn_CR_CONNECT 0x04
801 #define Sn_CR_DISCON 0x08
806 #define Sn_CR_CLOSE 0x10
813 #define Sn_CR_SEND 0x20
822 #define Sn_CR_SEND_MAC 0x21
829 #define Sn_CR_SEND_KEEP 0x22
836 #define Sn_CR_RECV 0x40
843 #define Sn_IR_SENDOK 0x10
848 #define Sn_IR_TIMEOUT 0x08
853 #define Sn_IR_RECV 0x04
858 #define Sn_IR_DISCON 0x02
863 #define Sn_IR_CON 0x01
872 #define SOCK_CLOSED 0x00
879 #define SOCK_INIT 0x13
886 #define SOCK_LISTEN 0x14
894 #define SOCK_SYNSENT 0x15
901 #define SOCK_SYNRECV 0x16
909 #define SOCK_ESTABLISHED 0x17
916 #define SOCK_FIN_WAIT 0x18
923 #define SOCK_CLOSING 0x1A
930 #define SOCK_TIME_WAIT 0x1B
937 #define SOCK_CLOSE_WAIT 0x1C
943 #define SOCK_LAST_ACK 0x1D
950 #define SOCK_UDP 0x22
958 #define SOCK_MACRAW 0x42
962 #define IPPROTO_IP 0 //< Dummy for IP
963 #define IPPROTO_ICMP 1 //< Control message protocol
964 #define IPPROTO_IGMP 2 //< Internet group management protocol
965 #define IPPROTO_GGP 3 //< Gateway^2 (deprecated)
966 #define IPPROTO_TCP 6 //< TCP
967 #define IPPROTO_PUP 12 //< PUP
968 #define IPPROTO_UDP 17 //< UDP
969 #define IPPROTO_IDP 22 //< XNS idp
970 #define IPPROTO_ND 77 //< UNOFFICIAL net disk protocol
971 #define IPPROTO_RAW 255 //< Raw IP packet
1107 void setMR(uint8_t mr);
1114 uint8_t
getMR(
void);
1122 void setGAR(uint8_t* gar);
1129 void getGAR(uint8_t* gar);
1197 void setIR(uint8_t ir);
1204 uint8_t
getIR(
void);
1212 void setIMR(uint8_t imr);
1227 void setSIR(uint8_t sir);
1257 void setRTR(uint16_t rtr);
1272 void setRCR(uint8_t rcr);
1397 void setSn_MR(uint8_t sn, uint8_t mr);
1412 void setSn_CR(uint8_t sn, uint8_t cr);
1427 void setSn_IR(uint8_t sn, uint8_t ir);
1443 void setSn_IMR(uint8_t sn, uint8_t imr);
1544 void setSn_TOS(uint8_t sn, uint8_t tos);
1560 void setSn_TTL(uint8_t sn, uint8_t ttl);
1708 void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
1725 void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len);