W5500
w5500.h
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1 //*****************************************************************************
2 //
39 //
40 //*****************************************************************************
41 
42 #ifndef _W5500_H_
43 #define _W5500_H_
44 
45 #include <stdint.h>
46 #include "wizchip_conf.h"
47 
48 
49 #define _W5500_SPI_READ_ (0x00 << 2) //< SPI interface Read operation in Control Phase
50 #define _W5500_SPI_WRITE_ (0x01 << 2) //< SPI interface Write operation in Control Phase
51 
52 #define WIZCHIP_CREG_BLOCK 0x00 //< Common register block
53 #define WIZCHIP_SREG_BLOCK(N) (1+4*N) //< Socket N register block
54 #define WIZCHIP_TXBUF_BLOCK(N) (2+4*N) //< Socket N Tx buffer address block
55 #define WIZCHIP_RXBUF_BLOCK(N) (3+4*N) //< Socket N Rx buffer address block
56 
57 #define WIZCHIP_OFFSET_INC(ADDR, N) (ADDR + (N<<8)) //< Increase offset address
58 
95 //----------------------------- W5500 Common Registers IOMAP -----------------------------
111 #define MR (_WIZCHIP_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_CREG_BLOCK << 3))
112 
117 #define GAR (_WIZCHIP_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_CREG_BLOCK << 3))
118 
123 #define SUBR (_WIZCHIP_IO_BASE_ + (0x0005 << 8) + (WIZCHIP_CREG_BLOCK << 3))
124 
129 #define SHAR (_WIZCHIP_IO_BASE_ + (0x0009 << 8) + (WIZCHIP_CREG_BLOCK << 3))
130 
135 #define SIPR (_WIZCHIP_IO_BASE_ + (0x000F << 8) + (WIZCHIP_CREG_BLOCK << 3))
136 
141 #define INTLEVEL (_WIZCHIP_IO_BASE_ + (0x0013 << 8) + (WIZCHIP_CREG_BLOCK << 3))
142 
157 #define IR (_WIZCHIP_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_CREG_BLOCK << 3))
158 
174 #define IMR (_WIZCHIP_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_CREG_BLOCK << 3))
175 
181 #define SIR (_WIZCHIP_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_CREG_BLOCK << 3))
182 
189 #define SIMR (_WIZCHIP_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_CREG_BLOCK << 3))
190 
198 #define RTR (_WIZCHIP_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_CREG_BLOCK << 3))
199 
205 #define RCR (_WIZCHIP_IO_BASE_ + (0x001B << 8) + (WIZCHIP_CREG_BLOCK << 3))
206 
211 #define PTIMER (_WIZCHIP_IO_BASE_ + (0x001C << 8) + (WIZCHIP_CREG_BLOCK << 3))
212 
217 #define PMAGIC (_WIZCHIP_IO_BASE_ + (0x001D << 8) + (WIZCHIP_CREG_BLOCK << 3))
218 
223 #define PHAR (_WIZCHIP_IO_BASE_ + (0x001E << 8) + (WIZCHIP_CREG_BLOCK << 3))
224 
229 #define PSID (_WIZCHIP_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_CREG_BLOCK << 3))
230 
235 #define PMRU (_WIZCHIP_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_CREG_BLOCK << 3))
236 
243 #define UIPR (_WIZCHIP_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_CREG_BLOCK << 3))
244 
251 #define UPORTR (_WIZCHIP_IO_BASE_ + (0x002C << 8) + (WIZCHIP_CREG_BLOCK << 3))
252 
257 #define PHYCFGR (_WIZCHIP_IO_BASE_ + (0x002E << 8) + (WIZCHIP_CREG_BLOCK << 3))
258 // Reserved (_WIZCHIP_IO_BASE_ + (0x002F << 8) + (WIZCHIP_CREG_BLOCK << 3))
259 // Reserved (_WIZCHIP_IO_BASE_ + (0x0030 << 8) + (WIZCHIP_CREG_BLOCK << 3))
260 // Reserved (_WIZCHIP_IO_BASE_ + (0x0031 << 8) + (WIZCHIP_CREG_BLOCK << 3))
261 // Reserved (_WIZCHIP_IO_BASE_ + (0x0032 << 8) + (WIZCHIP_CREG_BLOCK << 3))
262 // Reserved (_WIZCHIP_IO_BASE_ + (0x0033 << 8) + (WIZCHIP_CREG_BLOCK << 3))
263 // Reserved (_WIZCHIP_IO_BASE_ + (0x0034 << 8) + (WIZCHIP_CREG_BLOCK << 3))
264 // Reserved (_WIZCHIP_IO_BASE_ + (0x0035 << 8) + (WIZCHIP_CREG_BLOCK << 3))
265 // Reserved (_WIZCHIP_IO_BASE_ + (0x0036 << 8) + (WIZCHIP_CREG_BLOCK << 3))
266 // Reserved (_WIZCHIP_IO_BASE_ + (0x0037 << 8) + (WIZCHIP_CREG_BLOCK << 3))
267 // Reserved (_WIZCHIP_IO_BASE_ + (0x0038 << 8) + (WIZCHIP_CREG_BLOCK << 3))
273 #define VERSIONR (_WIZCHIP_IO_BASE_ + (0x0039 << 8) + (WIZCHIP_CREG_BLOCK << 3))
274 
275 
276 //----------------------------- W5500 Socket Registers IOMAP -----------------------------
307 #define Sn_MR(N) (_WIZCHIP_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
308 
325 #define Sn_CR(N) (_WIZCHIP_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
326 
342 #define Sn_IR(N) (_WIZCHIP_IO_BASE_ + (0x0002 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
343 
364 #define Sn_SR(N) (_WIZCHIP_IO_BASE_ + (0x0003 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
365 
371 #define Sn_PORT(N) (_WIZCHIP_IO_BASE_ + (0x0004 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
372 
378 #define Sn_DHAR(N) (_WIZCHIP_IO_BASE_ + (0x0006 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
379 
387 #define Sn_DIPR(N) (_WIZCHIP_IO_BASE_ + (0x000C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
388 
396 #define Sn_DPORT(N) (_WIZCHIP_IO_BASE_ + (0x0010 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
397 
402 #define Sn_MSSR(N) (_WIZCHIP_IO_BASE_ + (0x0012 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
403 // Reserved (_WIZCHIP_IO_BASE_ + (0x0014 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
410 #define Sn_TOS(N) (_WIZCHIP_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
411 
417 #define Sn_TTL(N) (_WIZCHIP_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
418 // Reserved (_WIZCHIP_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
419 // Reserved (_WIZCHIP_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
420 // Reserved (_WIZCHIP_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
421 // Reserved (_WIZCHIP_IO_BASE_ + (0x001A << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
422 // Reserved (_WIZCHIP_IO_BASE_ + (0x001B << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
423 // Reserved (_WIZCHIP_IO_BASE_ + (0x001C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
424 // Reserved (_WIZCHIP_IO_BASE_ + (0x001D << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
435 #define Sn_RXBUF_SIZE(N) (_WIZCHIP_IO_BASE_ + (0x001E << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
436 
445 #define Sn_TXBUF_SIZE(N) (_WIZCHIP_IO_BASE_ + (0x001F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
446 
455 #define Sn_TX_FSR(N) (_WIZCHIP_IO_BASE_ + (0x0020 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
456 
466 #define Sn_TX_RD(N) (_WIZCHIP_IO_BASE_ + (0x0022 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
467 
479 #define Sn_TX_WR(N) (_WIZCHIP_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
480 
487 #define Sn_RX_RSR(N) (_WIZCHIP_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
488 
499 #define Sn_RX_RD(N) (_WIZCHIP_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
500 
507 #define Sn_RX_WR(N) (_WIZCHIP_IO_BASE_ + (0x002A << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
508 
516 #define Sn_IMR(N) (_WIZCHIP_IO_BASE_ + (0x002C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
517 
522 #define Sn_FRAG(N) (_WIZCHIP_IO_BASE_ + (0x002D << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
523 
534 #define Sn_KPALVTR(N) (_WIZCHIP_IO_BASE_ + (0x002F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
535 //#define Sn_TSR(N) (_WIZCHIP_IO_BASE_ + (0x0030 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
536 
537 
538 //----------------------------- W5500 Register values -----------------------------
539 
540 /* MODE register values */
545 #define MR_RST 0x80
546 
555 #define MR_WOL 0x20
556 
562 #define MR_PB 0x10
563 
569 #define MR_PPPOE 0x08
570 
576 #define MR_FARP 0x02
577 
578 /* IR register values */
583 #define IR_CONFLICT 0x80
584 
589 #define IR_UNREACH 0x40
590 
594 #define IR_PPPoE 0x20
595 
599 #define IR_MP 0x10
600 
601 
602 /* PHYCFGR register value */
603 #define PHYCFGR_RST ~(1<<7) //< For PHY reset, must operate AND mask.
604 #define PHYCFGR_OPMD (1<<6) // Configre PHY with OPMDC value
605 #define PHYCFGR_OPMDC_ALLA (7<<3)
606 #define PHYCFGR_OPMDC_PDOWN (6<<3)
607 #define PHYCFGR_OPMDC_NA (5<<3)
608 #define PHYCFGR_OPMDC_100FA (4<<3)
609 #define PHYCFGR_OPMDC_100F (3<<3)
610 #define PHYCFGR_OPMDC_100H (2<<3)
611 #define PHYCFGR_OPMDC_10F (1<<3)
612 #define PHYCFGR_OPMDC_10H (0<<3)
613 #define PHYCFGR_DPX (1<<2)
614 #define PHYCFGR_SPD (1<<1)
615 #define PHYCFGR_LNK (1<<0);
616 
617 #define PHYCFGR_DPX_FULL 1
618 #define PHYCFGR_DPX_HALF 0
619 #define PHYCFGR_SPD_100 1
620 #define PHYCFGR_SDP_10 0
621 #define PHYCFGR_LNK_ON 1
622 #define PHYCFGR_LNK_OFF 0
623 
624 /* IMR register values */
630 #define IM_IR7 0x80
631 
636 #define IM_IR6 0x40
637 
642 #define IM_IR5 0x20
643 
648 #define IM_IR4 0x10
649 
650 /* Sn_MR Default values */
659 #define Sn_MR_MULTI 0x80
660 
667 #define Sn_MR_BCASTB 0x40
668 
676 #define Sn_MR_ND 0x20
677 
683 #define Sn_MR_UCASTB 0x10
684 
689 #define Sn_MR_MACRAW 0x04
690 //#define Sn_MR_IPRAW 0x03 /**< IP LAYER RAW SOCK */
695 #define Sn_MR_UDP 0x02
696 
700 #define Sn_MR_TCP 0x01
701 
705 #define Sn_MR_CLOSE 0x00
706 
707 /* Sn_MR values used with Sn_MR_MACRAW */
718 #define Sn_MR_MFEN Sn_MR_MULTI
719 
726 #define Sn_MR_MMB Sn_MR_ND
727 
733 #define Sn_MR_MIP6B Sn_MR_UCASTB
734 
735 /* Sn_MR value used with Sn_MR_UDP & Sn_MR_MULTI */
742 #define Sn_MR_MC Sn_MR_ND
743 
744 /* Sn_MR alternate values */
748 #define SOCK_STREAM Sn_MR_TCP
749 
752 #define SOCK_DGRAM Sn_MR_UDP
753 
754 
755 /* Sn_CR values */
768 #define Sn_CR_OPEN 0x01
769 
778 #define Sn_CR_LISTEN 0x02
779 
789 #define Sn_CR_CONNECT 0x04
790 
801 #define Sn_CR_DISCON 0x08
802 
806 #define Sn_CR_CLOSE 0x10
807 
813 #define Sn_CR_SEND 0x20
814 
822 #define Sn_CR_SEND_MAC 0x21
823 
829 #define Sn_CR_SEND_KEEP 0x22
830 
836 #define Sn_CR_RECV 0x40
837 
838 /* Sn_IR values */
843 #define Sn_IR_SENDOK 0x10
844 
848 #define Sn_IR_TIMEOUT 0x08
849 
853 #define Sn_IR_RECV 0x04
854 
858 #define Sn_IR_DISCON 0x02
859 
863 #define Sn_IR_CON 0x01
864 
865 
866 /* Sn_SR values */
872 #define SOCK_CLOSED 0x00
873 
879 #define SOCK_INIT 0x13
880 
886 #define SOCK_LISTEN 0x14
887 
894 #define SOCK_SYNSENT 0x15
895 
901 #define SOCK_SYNRECV 0x16
902 
909 #define SOCK_ESTABLISHED 0x17
910 
916 #define SOCK_FIN_WAIT 0x18
917 
923 #define SOCK_CLOSING 0x1A
924 
930 #define SOCK_TIME_WAIT 0x1B
931 
937 #define SOCK_CLOSE_WAIT 0x1C
938 
943 #define SOCK_LAST_ACK 0x1D
944 
950 #define SOCK_UDP 0x22
951 //#define SOCK_IPRAW 0x32 /**< IP raw mode socket */
958 #define SOCK_MACRAW 0x42
959 //#define SOCK_PPPOE 0x5F
960 
961 /* IP PROTOCOL */
962 #define IPPROTO_IP 0 //< Dummy for IP
963 #define IPPROTO_ICMP 1 //< Control message protocol
964 #define IPPROTO_IGMP 2 //< Internet group management protocol
965 #define IPPROTO_GGP 3 //< Gateway^2 (deprecated)
966 #define IPPROTO_TCP 6 //< TCP
967 #define IPPROTO_PUP 12 //< PUP
968 #define IPPROTO_UDP 17 //< UDP
969 #define IPPROTO_IDP 22 //< XNS idp
970 #define IPPROTO_ND 77 //< UNOFFICIAL net disk protocol
971 #define IPPROTO_RAW 255 //< Raw IP packet
972 
973 //----------------------------- Windowfull Control Values -----------------------------
974 //#define WINDOWFULL_FLAG_ON 1
975 //#define WINDOWFULL_FLAG_OFF 0
976 //#define WINDOWFULL_MAX_RETRY_NUM 3
977 //#define WINDOWFULL_WAIT_TIME 1000
978 
990 void WIZCHIP_CRITICAL_ENTER(void);
1002 void WIZCHIP_CRITICAL_EXIT(void);
1003 
1004 
1059 // Basic I/O Function //
1062 
1069 uint8_t WIZCHIP_READ (uint32_t AddrSel);
1077 void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb );
1085 void WIZCHIP_READ_BUF (uint32_t AddrSel, uint8_t* pBuf, uint16_t len);
1093 void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len);
1094 
1095 
1096 
1098 // Common Register I/O function //
1100 
1107 void setMR(uint8_t mr);
1114 uint8_t getMR(void);
1115 
1122 void setGAR(uint8_t* gar);
1129 void getGAR(uint8_t* gar);
1130 
1137 void setSUBR(uint8_t* subr);
1144 void getSUBR(uint8_t* subr);
1151 void setSHAR(uint8_t* shar);
1158 void getSHAR(uint8_t* shar);
1159 
1166 void setSIPR(uint8_t* sipr);
1167 
1174 void getSIPR(uint8_t* sipr);
1175 
1182 void setINTLEVEL(uint16_t intlevel);
1189 uint16_t getINTLEVEL(void);
1190 
1197 void setIR(uint8_t ir);
1204 uint8_t getIR(void);
1205 
1212 void setIMR(uint8_t imr);
1219 uint8_t getIMR(void);
1220 
1227 void setSIR(uint8_t sir);
1234 uint8_t getSIR(void);
1235 
1242 void setSIMR(uint8_t simr);
1249 uint8_t getSIMR(void);
1250 
1257 void setRTR(uint16_t rtr);
1264 uint16_t getRTR(void);
1265 
1272 void setRCR(uint8_t rcr);
1279 uint8_t getRCR(void);
1280 
1287 void setPTIMER(uint8_t ptimer);
1294 uint8_t getPTIMER(void);
1301 void setPMAGIC(uint8_t pmagic);
1308 uint8_t getPMAGIC(void);
1315 void setPHAR(uint8_t* phar);
1322 void getPHAR(uint8_t* phar);
1329 void setPSID(uint16_t psid);
1336 uint16_t getPSID(void);
1343 void setPMRU(uint16_t pmru);
1350 uint16_t getPMRU(void);
1351 
1357 void getUIPR(uint8_t* uipr);
1363 uint16_t getUPORTR(void);
1370 void setPHYCFGR(uint8_t phycfgr);
1377 uint8_t getPHYCFGR(void);
1378 
1384 uint8_t getVERSIONR(void);
1386 
1388 // Socket N register I/O function //
1390 
1397 void setSn_MR(uint8_t sn, uint8_t mr);
1404 uint8_t getSn_MR(uint8_t sn);
1412 void setSn_CR(uint8_t sn, uint8_t cr);
1419 uint8_t getSn_CR(uint8_t sn);
1427 void setSn_IR(uint8_t sn, uint8_t ir);
1434 uint8_t getSn_IR(uint8_t sn);
1435 
1443 void setSn_IMR(uint8_t sn, uint8_t imr);
1450 uint8_t getSn_IMR(uint8_t sn);
1451 
1457 uint8_t getSn_SR(uint8_t sn);
1458 
1466 void setSn_PORT(uint8_t sn, uint16_t port);
1473 uint16_t getSn_PORT(uint8_t sn);
1481 void setSn_DHAR(uint8_t sn, uint8_t* dhar);
1489 void getSn_DHAR(uint8_t sn, uint8_t* dhar);
1497 void setSn_DIPR(uint8_t sn, uint8_t* dipr);
1505 void getSn_DIPR(uint8_t sn, uint8_t* dipr);
1513 void setSn_DPORT(uint8_t sn, uint16_t dport);
1520 uint16_t getSn_DPORT(uint8_t sn);
1521 
1529 void setSn_MSSR(uint8_t sn, uint16_t mss);
1536 uint16_t getSn_MSSR(uint8_t sn);
1544 void setSn_TOS(uint8_t sn, uint8_t tos);
1551 uint8_t getSn_TOS(uint8_t sn);
1552 
1560 void setSn_TTL(uint8_t sn, uint8_t ttl);
1567 uint8_t getSn_TTL(uint8_t sn);
1575 void setSn_RXBUF_SIZE(uint8_t sn, uint8_t rxbufsize);
1582 uint8_t getSn_RXBUF_SIZE(uint8_t sn);
1590 void setSn_TXBUF_SIZE(uint8_t sn, uint8_t txbufsize);
1597 uint8_t getSn_TXBUF_SIZE(uint8_t sn);
1598 
1604 uint16_t getSn_TX_FSR(uint8_t sn);
1605 
1611 uint16_t getSn_TX_RD(uint8_t sn);
1619 void setSn_TX_WR(uint8_t sn, uint16_t txwr);
1626 uint16_t getSn_TX_WR(uint8_t sn);
1627 
1633 uint16_t getSn_RX_RSR(uint8_t sn);
1641 void setSn_RX_RD(uint8_t sn, uint16_t rxrd);
1648 uint16_t getSn_RX_RD(uint8_t sn);
1649 
1655 uint16_t getSn_RX_WR(uint8_t sn);
1663 void setSn_FRAG(uint8_t sn, uint16_t frag);
1670 uint16_t getSn_FRAG(uint8_t sn);
1678 void setSn_KPALVTR(uint8_t sn, uint8_t kpalvt);
1685 uint8_t getSn_KPALVTR(uint8_t sn);
1687 
1688 
1689 
1691 // Sn_TXBUF & Sn_RXBUF IO function //
1693 
1708 void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
1725 void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
1733 void wiz_recv_ignore(uint8_t sn, uint16_t len);
1734 
1735 /*
1736 uint8 incr_windowfull_retry_cnt(uint8 s);
1737 void init_windowfull_retry_cnt(uint8 s);
1738 */
1739 
1740 #endif