Socket APIs
w5500.h
Go to the documentation of this file.
1 //*****************************************************************************
2 //
39 //
40 //*****************************************************************************
41 
42 #ifndef _W5500_H_
43 #define _W5500_H_
44 
45 #include <stdint.h>
46 #include "Ethernet/wizchip_conf.h"
47 
48 #define _W5500_IO_BASE_ 0x00000000
49 
50 #define _W5500_SPI_READ_ (0x00 << 2) //< SPI interface Read operation in Control Phase
51 #define _W5500_SPI_WRITE_ (0x01 << 2) //< SPI interface Write operation in Control Phase
52 
53 #define WIZCHIP_CREG_BLOCK 0x00 //< Common register block
54 #define WIZCHIP_SREG_BLOCK(N) (1+4*N) //< Socket N register block
55 #define WIZCHIP_TXBUF_BLOCK(N) (2+4*N) //< Socket N Tx buffer address block
56 #define WIZCHIP_RXBUF_BLOCK(N) (3+4*N) //< Socket N Rx buffer address block
57 
58 #define WIZCHIP_OFFSET_INC(ADDR, N) (ADDR + (N<<8)) //< Increase offset address
59 
60 
62 // Definition For Legacy Chip Driver //
64 #define IINCHIP_READ(ADDR) WIZCHIP_READ(ADDR)
65 #define IINCHIP_WRITE(ADDR,VAL) WIZCHIP_WRITE(ADDR,VAL)
66 #define IINCHIP_READ_BUF(ADDR,BUF,LEN) WIZCHIP_READ_BUF(ADDR,BUF,LEN)
67 #define IINCHIP_WRITE_BUF(ADDR,BUF,LEN) WIZCHIP_WRITE(ADDR,BUF,LEN)
68 
69 //-------------------------- defgroup ---------------------------------
187 //------------------------------- defgroup end --------------------------------------------
188 //----------------------------- W5500 Common Registers IOMAP -----------------------------
204 #define MR (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_CREG_BLOCK << 3))
205 
211 #define GAR (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_CREG_BLOCK << 3))
212 
218 #define SUBR (_W5500_IO_BASE_ + (0x0005 << 8) + (WIZCHIP_CREG_BLOCK << 3))
219 
225 #define SHAR (_W5500_IO_BASE_ + (0x0009 << 8) + (WIZCHIP_CREG_BLOCK << 3))
226 
232 #define SIPR (_W5500_IO_BASE_ + (0x000F << 8) + (WIZCHIP_CREG_BLOCK << 3))
233 
239 #define INTLEVEL (_W5500_IO_BASE_ + (0x0013 << 8) + (WIZCHIP_CREG_BLOCK << 3))
240 
256 #define IR (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_CREG_BLOCK << 3))
257 
274 #define IMR (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_CREG_BLOCK << 3))
275 
282 #define SIR (_W5500_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_CREG_BLOCK << 3))
283 
291 #define SIMR (_W5500_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_CREG_BLOCK << 3))
292 
301 #define RTR (_W5500_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_CREG_BLOCK << 3))
302 
309 #define RCR (_W5500_IO_BASE_ + (0x001B << 8) + (WIZCHIP_CREG_BLOCK << 3))
310 
316 #define PTIMER (_W5500_IO_BASE_ + (0x001C << 8) + (WIZCHIP_CREG_BLOCK << 3))
317 
323 #define PMAGIC (_W5500_IO_BASE_ + (0x001D << 8) + (WIZCHIP_CREG_BLOCK << 3))
324 
330 #define PHAR (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_CREG_BLOCK << 3))
331 
337 #define PSID (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_CREG_BLOCK << 3))
338 
344 #define PMRU (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_CREG_BLOCK << 3))
345 
353 #define UIPR (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_CREG_BLOCK << 3))
354 
362 #define UPORTR (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_CREG_BLOCK << 3))
363 
369 #define PHYCFGR (_W5500_IO_BASE_ + (0x002E << 8) + (WIZCHIP_CREG_BLOCK << 3))
370 
371 // Reserved (_W5500_IO_BASE_ + (0x002F << 8) + (WIZCHIP_CREG_BLOCK << 3))
372 // Reserved (_W5500_IO_BASE_ + (0x0030 << 8) + (WIZCHIP_CREG_BLOCK << 3))
373 // Reserved (_W5500_IO_BASE_ + (0x0031 << 8) + (WIZCHIP_CREG_BLOCK << 3))
374 // Reserved (_W5500_IO_BASE_ + (0x0032 << 8) + (WIZCHIP_CREG_BLOCK << 3))
375 // Reserved (_W5500_IO_BASE_ + (0x0033 << 8) + (WIZCHIP_CREG_BLOCK << 3))
376 // Reserved (_W5500_IO_BASE_ + (0x0034 << 8) + (WIZCHIP_CREG_BLOCK << 3))
377 // Reserved (_W5500_IO_BASE_ + (0x0035 << 8) + (WIZCHIP_CREG_BLOCK << 3))
378 // Reserved (_W5500_IO_BASE_ + (0x0036 << 8) + (WIZCHIP_CREG_BLOCK << 3))
379 // Reserved (_W5500_IO_BASE_ + (0x0037 << 8) + (WIZCHIP_CREG_BLOCK << 3))
380 // Reserved (_W5500_IO_BASE_ + (0x0038 << 8) + (WIZCHIP_CREG_BLOCK << 3))
381 
387 #define VERSIONR (_W5500_IO_BASE_ + (0x0039 << 8) + (WIZCHIP_CREG_BLOCK << 3))
388 
389 
390 //----------------------------- W5500 Socket Registers IOMAP -----------------------------
421 #define Sn_MR(N) (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
422 
440 #define Sn_CR(N) (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
441 
458 #define Sn_IR(N) (_W5500_IO_BASE_ + (0x0002 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
459 
481 #define Sn_SR(N) (_W5500_IO_BASE_ + (0x0003 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
482 
489 #define Sn_PORT(N) (_W5500_IO_BASE_ + (0x0004 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
490 
497 #define Sn_DHAR(N) (_W5500_IO_BASE_ + (0x0006 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
498 
507 #define Sn_DIPR(N) (_W5500_IO_BASE_ + (0x000C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
508 
517 #define Sn_DPORT(N) (_W5500_IO_BASE_ + (0x0010 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
518 
524 #define Sn_MSSR(N) (_W5500_IO_BASE_ + (0x0012 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
525 
526 #define Sn_PROTO(N) (_W5500_IO_BASE_ + (0x0014 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
527 // Reserved (_W5500_IO_BASE_ + (0x0014 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
528 
535 #define Sn_TOS(N) (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
536 
542 #define Sn_TTL(N) (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
543 // Reserved (_W5500_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
544 // Reserved (_W5500_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
545 // Reserved (_W5500_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
546 // Reserved (_W5500_IO_BASE_ + (0x001A << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
547 // Reserved (_W5500_IO_BASE_ + (0x001B << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
548 // Reserved (_W5500_IO_BASE_ + (0x001C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
549 // Reserved (_W5500_IO_BASE_ + (0x001D << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
550 
561 #define Sn_RXBUF_SIZE(N) (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
562 
572 #define Sn_TXBUF_SIZE(N) (_W5500_IO_BASE_ + (0x001F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
573 
583 #define Sn_TX_FSR(N) (_W5500_IO_BASE_ + (0x0020 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
584 
595 #define Sn_TX_RD(N) (_W5500_IO_BASE_ + (0x0022 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
596 
609 #define Sn_TX_WR(N) (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
610 
618 #define Sn_RX_RSR(N) (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
619 
631 #define Sn_RX_RD(N) (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
632 
640 #define Sn_RX_WR(N) (_W5500_IO_BASE_ + (0x002A << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
641 
650 #define Sn_IMR(N) (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
651 
657 #define Sn_FRAG(N) (_W5500_IO_BASE_ + (0x002D << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
658 
670 #define Sn_KPALVTR(N) (_W5500_IO_BASE_ + (0x002F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
671 
672 //#define Sn_TSR(N) (_W5500_IO_BASE_ + (0x0030 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
673 
674 
675 //----------------------------- W5500 Register values -----------------------------
676 
677 /* MODE register values */
682 #define MR_RST 0x80
683 
693 #define MR_WOL 0x20
694 
701 #define MR_PB 0x10
702 
709 #define MR_PPPOE 0x08
710 
717 #define MR_FARP 0x02
718 
719 /* IR register values */
724 #define IR_CONFLICT 0x80
725 
731 #define IR_UNREACH 0x40
732 
737 #define IR_PPPoE 0x20
738 
743 #define IR_MP 0x10
744 
745 
746 /* PHYCFGR register value */
747 #define PHYCFGR_RST ~(1<<7) //< For PHY reset, must operate AND mask.
748 #define PHYCFGR_OPMD (1<<6) // Configre PHY with OPMDC value
749 #define PHYCFGR_OPMDC_ALLA (7<<3)
750 #define PHYCFGR_OPMDC_PDOWN (6<<3)
751 #define PHYCFGR_OPMDC_NA (5<<3)
752 #define PHYCFGR_OPMDC_100FA (4<<3)
753 #define PHYCFGR_OPMDC_100F (3<<3)
754 #define PHYCFGR_OPMDC_100H (2<<3)
755 #define PHYCFGR_OPMDC_10F (1<<3)
756 #define PHYCFGR_OPMDC_10H (0<<3)
757 #define PHYCFGR_DPX_FULL (1<<2)
758 #define PHYCFGR_DPX_HALF (0<<2)
759 #define PHYCFGR_SPD_100 (1<<1)
760 #define PHYCFGR_SPD_10 (0<<1)
761 #define PHYCFGR_LNK_ON (1<<0)
762 #define PHYCFGR_LNK_OFF (0<<0)
763 
764 /* IMR register values */
770 #define IM_IR7 0x80
771 
777 #define IM_IR6 0x40
778 
784 #define IM_IR5 0x20
785 
791 #define IM_IR4 0x10
792 
793 /* Sn_MR Default values */
802 #define Sn_MR_MULTI 0x80
803 
811 #define Sn_MR_BCASTB 0x40
812 
821 #define Sn_MR_ND 0x20
822 
829 #define Sn_MR_UCASTB 0x10
830 
836 #define Sn_MR_MACRAW 0x04
837 
838 #define Sn_MR_IPRAW 0x03
844 #define Sn_MR_UDP 0x02
845 
850 #define Sn_MR_TCP 0x01
851 
856 #define Sn_MR_CLOSE 0x00
857 
858 /* Sn_MR values used with Sn_MR_MACRAW */
869 #define Sn_MR_MFEN Sn_MR_MULTI
870 
878 #define Sn_MR_MMB Sn_MR_ND
879 
886 #define Sn_MR_MIP6B Sn_MR_UCASTB
887 
888 /* Sn_MR value used with Sn_MR_UDP & Sn_MR_MULTI */
895 #define Sn_MR_MC Sn_MR_ND
896 
897 /* Sn_MR alternate values */
901 #define SOCK_STREAM Sn_MR_TCP
902 
906 #define SOCK_DGRAM Sn_MR_UDP
907 
908 
909 /* Sn_CR values */
922 #define Sn_CR_OPEN 0x01
923 
933 #define Sn_CR_LISTEN 0x02
934 
945 #define Sn_CR_CONNECT 0x04
946 
958 #define Sn_CR_DISCON 0x08
959 
964 #define Sn_CR_CLOSE 0x10
965 
972 #define Sn_CR_SEND 0x20
973 
982 #define Sn_CR_SEND_MAC 0x21
983 
990 #define Sn_CR_SEND_KEEP 0x22
991 
998 #define Sn_CR_RECV 0x40
999 
1000 /* Sn_IR values */
1005 #define Sn_IR_SENDOK 0x10
1006 
1011 #define Sn_IR_TIMEOUT 0x08
1012 
1017 #define Sn_IR_RECV 0x04
1018 
1023 #define Sn_IR_DISCON 0x02
1024 
1029 #define Sn_IR_CON 0x01
1030 
1031 /* Sn_SR values */
1037 #define SOCK_CLOSED 0x00
1038 
1045 #define SOCK_INIT 0x13
1046 
1053 #define SOCK_LISTEN 0x14
1054 
1062 #define SOCK_SYNSENT 0x15
1063 
1070 #define SOCK_SYNRECV 0x16
1071 
1079 #define SOCK_ESTABLISHED 0x17
1080 
1087 #define SOCK_FIN_WAIT 0x18
1088 
1095 #define SOCK_CLOSING 0x1A
1096 
1103 #define SOCK_TIME_WAIT 0x1B
1104 
1111 #define SOCK_CLOSE_WAIT 0x1C
1112 
1118 #define SOCK_LAST_ACK 0x1D
1119 
1126 #define SOCK_UDP 0x22
1127 
1128 #define SOCK_IPRAW 0x32
1136 #define SOCK_MACRAW 0x42
1137 
1138 //#define SOCK_PPPOE 0x5F
1139 
1140 /* IP PROTOCOL */
1141 #define IPPROTO_IP 0 //< Dummy for IP
1142 #define IPPROTO_ICMP 1 //< Control message protocol
1143 #define IPPROTO_IGMP 2 //< Internet group management protocol
1144 #define IPPROTO_GGP 3 //< Gateway^2 (deprecated)
1145 #define IPPROTO_TCP 6 //< TCP
1146 #define IPPROTO_PUP 12 //< PUP
1147 #define IPPROTO_UDP 17 //< UDP
1148 #define IPPROTO_IDP 22 //< XNS idp
1149 #define IPPROTO_ND 77 //< UNOFFICIAL net disk protocol
1150 #define IPPROTO_RAW 255 //< Raw IP packet
1151 
1152 
1164 #define WIZCHIP_CRITICAL_ENTER() WIZCHIP.CRIS._enter()
1165 
1177 #define WIZCHIP_CRITICAL_EXIT() WIZCHIP.CRIS._exit()
1178 
1179 
1180 
1182 // Basic I/O Function //
1184 
1191 uint8_t WIZCHIP_READ (uint32_t AddrSel);
1192 
1200 void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb );
1201 
1209 void WIZCHIP_READ_BUF (uint32_t AddrSel, uint8_t* pBuf, uint16_t len);
1210 
1218 void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len);
1219 
1221 // Common Register I/O function //
1223 
1229 #define setMR(mr) \
1230  WIZCHIP_WRITE(MR,mr)
1231 
1232 
1239 #define getMR() \
1240  WIZCHIP_READ(MR)
1241 
1248 #define setGAR(gar) \
1249  WIZCHIP_WRITE_BUF(GAR,gar,4)
1250 
1257 #define getGAR(gar) \
1258  WIZCHIP_READ_BUF(GAR,gar,4)
1259 
1266 #define setSUBR(subr) \
1267  WIZCHIP_WRITE_BUF(SUBR, subr,4)
1268 
1269 
1276 #define getSUBR(subr) \
1277  WIZCHIP_READ_BUF(SUBR, subr, 4)
1278 
1285 #define setSHAR(shar) \
1286  WIZCHIP_WRITE_BUF(SHAR, shar, 6)
1287 
1294 #define getSHAR(shar) \
1295  WIZCHIP_READ_BUF(SHAR, shar, 6)
1296 
1303 #define setSIPR(sipr) \
1304  WIZCHIP_WRITE_BUF(SIPR, sipr, 4)
1305 
1312 #define getSIPR(sipr) \
1313  WIZCHIP_READ_BUF(SIPR, sipr, 4)
1314 
1321 #define setINTLEVEL(intlevel) {\
1322  WIZCHIP_WRITE(INTLEVEL, (uint8_t)(intlevel >> 8)); \
1323  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(INTLEVEL,1), (uint8_t) intlevel); \
1324  }
1325 
1326 
1333 #define getINTLEVEL() \
1334  ((WIZCHIP_READ(INTLEVEL) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(INTLEVEL,1)))
1335 
1342 #define setIR(ir) \
1343  WIZCHIP_WRITE(IR, (ir & 0xF0))
1344 
1351 #define getIR() \
1352  (WIZCHIP_READ(IR) & 0xF0)
1353 
1359 #define setIMR(imr) \
1360  WIZCHIP_WRITE(IMR, imr)
1361 
1368 #define getIMR() \
1369  WIZCHIP_READ(IMR)
1370 
1371 
1378 #define setSIR(sir) \
1379  WIZCHIP_WRITE(SIR, sir)
1380 
1387 #define getSIR() \
1388  WIZCHIP_READ(SIR)
1389 
1395 #define setSIMR(simr) \
1396  WIZCHIP_WRITE(SIMR, simr)
1397 
1404 #define getSIMR() \
1405  WIZCHIP_READ(SIMR)
1406 
1413 #define setRTR(rtr) {\
1414  WIZCHIP_WRITE(RTR, (uint8_t)(rtr >> 8)); \
1415  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(RTR,1), (uint8_t) rtr); \
1416  }
1417 
1424 #define getRTR() \
1425  ((WIZCHIP_READ(RTR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(RTR,1)))
1426 
1433 #define setRCR(rcr) \
1434  WIZCHIP_WRITE(RCR, rcr)
1435 
1442 #define getRCR() \
1443  WIZCHIP_READ(RCR)
1444 
1445 //================================================== test done ===========================================================
1446 
1453 #define setPTIMER(ptimer) \
1454  WIZCHIP_WRITE(PTIMER, ptimer)
1455 
1462 #define getPTIMER() \
1463  WIZCHIP_READ(PTIMER)
1464 
1471 #define setPMAGIC(pmagic) \
1472  WIZCHIP_WRITE(PMAGIC, pmagic)
1473 
1480 #define getPMAGIC() \
1481  WIZCHIP_READ(PMAGIC)
1482 
1489 #define setPHAR(phar) \
1490  WIZCHIP_WRITE_BUF(PHAR, phar, 6)
1491 
1498 #define getPHAR(phar) \
1499  WIZCHIP_READ_BUF(PHAR, phar, 6)
1500 
1507 #define setPSID(psid) {\
1508  WIZCHIP_WRITE(PSID, (uint8_t)(psid >> 8)); \
1509  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(PSID,1), (uint8_t) psid); \
1510  }
1511 
1518 //uint16_t getPSID(void);
1519 #define getPSID() \
1520  ((WIZCHIP_READ(PSID) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PSID,1)))
1521 
1528 #define setPMRU(pmru) { \
1529  WIZCHIP_WRITE(PMRU, (uint8_t)(pmru>>8)); \
1530  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(PMRU,1), (uint8_t) pmru); \
1531  }
1532 
1539 #define getPMRU() \
1540  ((WIZCHIP_READ(PMRU) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PMRU,1)))
1541 
1547 #define getUIPR(uipr) \
1548  WIZCHIP_READ_BUF(UIPR,uipr,6)
1549 
1555 #define getUPORTR() \
1556  ((WIZCHIP_READ(UPORTR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(UPORTR,1)))
1557 
1564 #define setPHYCFGR(phycfgr) \
1565  WIZCHIP_WRITE(PHYCFGR, phycfgr)
1566 
1573 #define getPHYCFGR() \
1574  WIZCHIP_READ(PHYCFGR)
1575 
1581 #define getVERSIONR() \
1582  WIZCHIP_READ(VERSIONR)
1583 
1585 
1587 // Socket N register I/O function //
1589 
1596 #define setSn_MR(sn, mr) \
1597  WIZCHIP_WRITE(Sn_MR(sn),mr)
1598 
1606 #define getSn_MR(sn) \
1607  WIZCHIP_READ(Sn_MR(sn))
1608 
1616 #define setSn_CR(sn, cr) \
1617  WIZCHIP_WRITE(Sn_CR(sn), cr)
1618 
1626 #define getSn_CR(sn) \
1627  WIZCHIP_READ(Sn_CR(sn))
1628 
1636 #define setSn_IR(sn, ir) \
1637  WIZCHIP_WRITE(Sn_IR(sn), (ir & 0x1F))
1638 
1646 #define getSn_IR(sn) \
1647  (WIZCHIP_READ(Sn_IR(sn)) & 0x1F)
1648 
1656 #define setSn_IMR(sn, imr) \
1657  WIZCHIP_WRITE(Sn_IMR(sn), (imr & 0x1F))
1658 
1666 #define getSn_IMR(sn) \
1667  (WIZCHIP_READ(Sn_IMR(sn)) & 0x1F)
1668 
1675 #define getSn_SR(sn) \
1676  WIZCHIP_READ(Sn_SR(sn))
1677 
1685 #define setSn_PORT(sn, port) { \
1686  WIZCHIP_WRITE(Sn_PORT(sn), (uint8_t)(port >> 8)); \
1687  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1), (uint8_t) port); \
1688  }
1689 
1697 #define getSn_PORT(sn) \
1698  ((WIZCHIP_READ(Sn_PORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1)))
1699 
1707 #define setSn_DHAR(sn, dhar) \
1708  WIZCHIP_WRITE_BUF(Sn_DHAR(sn), dhar, 6)
1709 
1717 #define getSn_DHAR(sn, dhar) \
1718  WIZCHIP_READ_BUF(Sn_DHAR(sn), dhar, 6)
1719 
1727 #define setSn_DIPR(sn, dipr) \
1728  WIZCHIP_WRITE_BUF(Sn_DIPR(sn), dipr, 4)
1729 
1737 #define getSn_DIPR(sn, dipr) \
1738  WIZCHIP_READ_BUF(Sn_DIPR(sn), dipr, 4)
1739 
1747 #define setSn_DPORT(sn, dport) { \
1748  WIZCHIP_WRITE(Sn_DPORT(sn), (uint8_t) (dport>>8)); \
1749  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1), (uint8_t) dport); \
1750  }
1751 
1759 #define getSn_DPORT(sn) \
1760  ((WIZCHIP_READ(Sn_DPORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1)))
1761 
1769 #define setSn_MSSR(sn, mss) { \
1770  WIZCHIP_WRITE(Sn_MSSR(sn), (uint8_t)(mss>>8)); \
1771  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1), (uint8_t) mss); \
1772  }
1773 
1781 #define getSn_MSSR(sn) \
1782  ((WIZCHIP_READ(Sn_MSSR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1)))
1783 
1791 #define setSn_TOS(sn, tos) \
1792  WIZCHIP_WRITE(Sn_TOS(sn), tos)
1793 
1801 #define getSn_TOS(sn) \
1802  WIZCHIP_READ(Sn_TOS(sn))
1803 
1811 #define setSn_TTL(sn, ttl) \
1812  WIZCHIP_WRITE(Sn_TTL(sn), ttl)
1813 
1814 
1822 #define getSn_TTL(sn) \
1823  WIZCHIP_READ(Sn_TTL(sn))
1824 
1825 
1833 #define setSn_RXBUF_SIZE(sn, rxbufsize) \
1834  WIZCHIP_WRITE(Sn_RXBUF_SIZE(sn),rxbufsize)
1835 
1836 
1844 #define getSn_RXBUF_SIZE(sn) \
1845  WIZCHIP_READ(Sn_RXBUF_SIZE(sn))
1846 
1854 #define setSn_TXBUF_SIZE(sn, txbufsize) \
1855  WIZCHIP_WRITE(Sn_TXBUF_SIZE(sn), txbufsize)
1856 
1864 #define getSn_TXBUF_SIZE(sn) \
1865  WIZCHIP_READ(Sn_TXBUF_SIZE(sn))
1866 
1873 uint16_t getSn_TX_FSR(uint8_t sn);
1874 
1881 #define getSn_TX_RD(sn) \
1882  ((WIZCHIP_READ(Sn_TX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_RD(sn),1)))
1883 
1891 #define setSn_TX_WR(sn, txwr) { \
1892  WIZCHIP_WRITE(Sn_TX_WR(sn), (uint8_t)(txwr>>8)); \
1893  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1), (uint8_t) txwr); \
1894  }
1895 
1903 #define getSn_TX_WR(sn) \
1904  ((WIZCHIP_READ(Sn_TX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1)))
1905 
1906 
1913 uint16_t getSn_RX_RSR(uint8_t sn);
1914 
1915 
1923 #define setSn_RX_RD(sn, rxrd) { \
1924  WIZCHIP_WRITE(Sn_RX_RD(sn), (uint8_t)(rxrd>>8)); \
1925  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1), (uint8_t) rxrd); \
1926  }
1927 
1935 #define getSn_RX_RD(sn) \
1936  ((WIZCHIP_READ(Sn_RX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1)))
1937 
1944 #define getSn_RX_WR(sn) \
1945  ((WIZCHIP_READ(Sn_RX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1)))
1946 
1947 
1955 #define setSn_FRAG(sn, frag) { \
1956  WIZCHIP_WRITE(Sn_FRAG(sn), (uint8_t)(frag >>8)); \
1957  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1), (uint8_t) frag); \
1958  }
1959 
1967 #define getSn_FRAG(sn) \
1968  ((WIZCHIP_READ(Sn_FRAG(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1)))
1969 
1977 #define setSn_KPALVTR(sn, kpalvt) \
1978  WIZCHIP_WRITE(Sn_KPALVTR(sn), kpalvt)
1979 
1987 #define getSn_KPALVTR(sn) \
1988  WIZCHIP_READ(Sn_KPALVTR(sn))
1989 
1991 
1993 // Sn_TXBUF & Sn_RXBUF IO function //
1995 
2000 #define getSn_RxMAX(sn) \
2001  (getSn_RXBUF_SIZE(sn) << 10)
2002 
2008 //uint16_t getSn_TxMAX(uint8_t sn);
2009 #define getSn_TxMAX(sn) \
2010  (getSn_TXBUF_SIZE(sn) << 10)
2011 
2027 void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
2028 
2044 void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
2045 
2053 void wiz_recv_ignore(uint8_t sn, uint16_t len);
2054 
2055 #endif // _W5500_H_