48 #define _W5500_IO_BASE_ 0x00000000
50 #define _W5500_SPI_READ_ (0x00 << 2) //< SPI interface Read operation in Control Phase
51 #define _W5500_SPI_WRITE_ (0x01 << 2) //< SPI interface Write operation in Control Phase
53 #define WIZCHIP_CREG_BLOCK 0x00 //< Common register block
54 #define WIZCHIP_SREG_BLOCK(N) (1+4*N) //< Socket N register block
55 #define WIZCHIP_TXBUF_BLOCK(N) (2+4*N) //< Socket N Tx buffer address block
56 #define WIZCHIP_RXBUF_BLOCK(N) (3+4*N) //< Socket N Rx buffer address block
58 #define WIZCHIP_OFFSET_INC(ADDR, N) (ADDR + (N<<8)) //< Increase offset address
64 #define IINCHIP_READ(ADDR) WIZCHIP_READ(ADDR)
65 #define IINCHIP_WRITE(ADDR,VAL) WIZCHIP_WRITE(ADDR,VAL)
66 #define IINCHIP_READ_BUF(ADDR,BUF,LEN) WIZCHIP_READ_BUF(ADDR,BUF,LEN)
67 #define IINCHIP_WRITE_BUF(ADDR,BUF,LEN) WIZCHIP_WRITE(ADDR,BUF,LEN)
204 #define MR (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_CREG_BLOCK << 3))
211 #define GAR (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_CREG_BLOCK << 3))
218 #define SUBR (_W5500_IO_BASE_ + (0x0005 << 8) + (WIZCHIP_CREG_BLOCK << 3))
225 #define SHAR (_W5500_IO_BASE_ + (0x0009 << 8) + (WIZCHIP_CREG_BLOCK << 3))
232 #define SIPR (_W5500_IO_BASE_ + (0x000F << 8) + (WIZCHIP_CREG_BLOCK << 3))
239 #define INTLEVEL (_W5500_IO_BASE_ + (0x0013 << 8) + (WIZCHIP_CREG_BLOCK << 3))
256 #define IR (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_CREG_BLOCK << 3))
274 #define IMR (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_CREG_BLOCK << 3))
282 #define SIR (_W5500_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_CREG_BLOCK << 3))
291 #define SIMR (_W5500_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_CREG_BLOCK << 3))
301 #define RTR (_W5500_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_CREG_BLOCK << 3))
309 #define RCR (_W5500_IO_BASE_ + (0x001B << 8) + (WIZCHIP_CREG_BLOCK << 3))
316 #define PTIMER (_W5500_IO_BASE_ + (0x001C << 8) + (WIZCHIP_CREG_BLOCK << 3))
323 #define PMAGIC (_W5500_IO_BASE_ + (0x001D << 8) + (WIZCHIP_CREG_BLOCK << 3))
330 #define PHAR (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_CREG_BLOCK << 3))
337 #define PSID (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_CREG_BLOCK << 3))
344 #define PMRU (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_CREG_BLOCK << 3))
353 #define UIPR (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_CREG_BLOCK << 3))
362 #define UPORTR (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_CREG_BLOCK << 3))
369 #define PHYCFGR (_W5500_IO_BASE_ + (0x002E << 8) + (WIZCHIP_CREG_BLOCK << 3))
387 #define VERSIONR (_W5500_IO_BASE_ + (0x0039 << 8) + (WIZCHIP_CREG_BLOCK << 3))
421 #define Sn_MR(N) (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
440 #define Sn_CR(N) (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
458 #define Sn_IR(N) (_W5500_IO_BASE_ + (0x0002 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
481 #define Sn_SR(N) (_W5500_IO_BASE_ + (0x0003 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
489 #define Sn_PORT(N) (_W5500_IO_BASE_ + (0x0004 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
497 #define Sn_DHAR(N) (_W5500_IO_BASE_ + (0x0006 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
507 #define Sn_DIPR(N) (_W5500_IO_BASE_ + (0x000C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
517 #define Sn_DPORT(N) (_W5500_IO_BASE_ + (0x0010 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
524 #define Sn_MSSR(N) (_W5500_IO_BASE_ + (0x0012 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
526 #define Sn_PROTO(N) (_W5500_IO_BASE_ + (0x0014 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
535 #define Sn_TOS(N) (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
542 #define Sn_TTL(N) (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
561 #define Sn_RXBUF_SIZE(N) (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
572 #define Sn_TXBUF_SIZE(N) (_W5500_IO_BASE_ + (0x001F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
583 #define Sn_TX_FSR(N) (_W5500_IO_BASE_ + (0x0020 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
595 #define Sn_TX_RD(N) (_W5500_IO_BASE_ + (0x0022 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
609 #define Sn_TX_WR(N) (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
618 #define Sn_RX_RSR(N) (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
631 #define Sn_RX_RD(N) (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
640 #define Sn_RX_WR(N) (_W5500_IO_BASE_ + (0x002A << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
650 #define Sn_IMR(N) (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
657 #define Sn_FRAG(N) (_W5500_IO_BASE_ + (0x002D << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
670 #define Sn_KPALVTR(N) (_W5500_IO_BASE_ + (0x002F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
709 #define MR_PPPOE 0x08
724 #define IR_CONFLICT 0x80
731 #define IR_UNREACH 0x40
737 #define IR_PPPoE 0x20
747 #define PHYCFGR_RST ~(1<<7) //< For PHY reset, must operate AND mask.
748 #define PHYCFGR_OPMD (1<<6) // Configre PHY with OPMDC value
749 #define PHYCFGR_OPMDC_ALLA (7<<3)
750 #define PHYCFGR_OPMDC_PDOWN (6<<3)
751 #define PHYCFGR_OPMDC_NA (5<<3)
752 #define PHYCFGR_OPMDC_100FA (4<<3)
753 #define PHYCFGR_OPMDC_100F (3<<3)
754 #define PHYCFGR_OPMDC_100H (2<<3)
755 #define PHYCFGR_OPMDC_10F (1<<3)
756 #define PHYCFGR_OPMDC_10H (0<<3)
757 #define PHYCFGR_DPX_FULL (1<<2)
758 #define PHYCFGR_DPX_HALF (0<<2)
759 #define PHYCFGR_SPD_100 (1<<1)
760 #define PHYCFGR_SPD_10 (0<<1)
761 #define PHYCFGR_LNK_ON (1<<0)
762 #define PHYCFGR_LNK_OFF (0<<0)
802 #define Sn_MR_MULTI 0x80
811 #define Sn_MR_BCASTB 0x40
821 #define Sn_MR_ND 0x20
829 #define Sn_MR_UCASTB 0x10
836 #define Sn_MR_MACRAW 0x04
838 #define Sn_MR_IPRAW 0x03
844 #define Sn_MR_UDP 0x02
850 #define Sn_MR_TCP 0x01
856 #define Sn_MR_CLOSE 0x00
869 #define Sn_MR_MFEN Sn_MR_MULTI
878 #define Sn_MR_MMB Sn_MR_ND
886 #define Sn_MR_MIP6B Sn_MR_UCASTB
895 #define Sn_MR_MC Sn_MR_ND
901 #define SOCK_STREAM Sn_MR_TCP
906 #define SOCK_DGRAM Sn_MR_UDP
922 #define Sn_CR_OPEN 0x01
933 #define Sn_CR_LISTEN 0x02
945 #define Sn_CR_CONNECT 0x04
958 #define Sn_CR_DISCON 0x08
964 #define Sn_CR_CLOSE 0x10
972 #define Sn_CR_SEND 0x20
982 #define Sn_CR_SEND_MAC 0x21
990 #define Sn_CR_SEND_KEEP 0x22
998 #define Sn_CR_RECV 0x40
1005 #define Sn_IR_SENDOK 0x10
1011 #define Sn_IR_TIMEOUT 0x08
1017 #define Sn_IR_RECV 0x04
1023 #define Sn_IR_DISCON 0x02
1029 #define Sn_IR_CON 0x01
1037 #define SOCK_CLOSED 0x00
1045 #define SOCK_INIT 0x13
1053 #define SOCK_LISTEN 0x14
1062 #define SOCK_SYNSENT 0x15
1070 #define SOCK_SYNRECV 0x16
1079 #define SOCK_ESTABLISHED 0x17
1087 #define SOCK_FIN_WAIT 0x18
1095 #define SOCK_CLOSING 0x1A
1103 #define SOCK_TIME_WAIT 0x1B
1111 #define SOCK_CLOSE_WAIT 0x1C
1118 #define SOCK_LAST_ACK 0x1D
1126 #define SOCK_UDP 0x22
1128 #define SOCK_IPRAW 0x32
1136 #define SOCK_MACRAW 0x42
1141 #define IPPROTO_IP 0 //< Dummy for IP
1142 #define IPPROTO_ICMP 1 //< Control message protocol
1143 #define IPPROTO_IGMP 2 //< Internet group management protocol
1144 #define IPPROTO_GGP 3 //< Gateway^2 (deprecated)
1145 #define IPPROTO_TCP 6 //< TCP
1146 #define IPPROTO_PUP 12 //< PUP
1147 #define IPPROTO_UDP 17 //< UDP
1148 #define IPPROTO_IDP 22 //< XNS idp
1149 #define IPPROTO_ND 77 //< UNOFFICIAL net disk protocol
1150 #define IPPROTO_RAW 255 //< Raw IP packet
1164 #define WIZCHIP_CRITICAL_ENTER() WIZCHIP.CRIS._enter()
1177 #define WIZCHIP_CRITICAL_EXIT() WIZCHIP.CRIS._exit()
1230 WIZCHIP_WRITE(MR,mr)
1248 #define setGAR(gar) \
1249 WIZCHIP_WRITE_BUF(GAR,gar,4)
1257 #define getGAR(gar) \
1258 WIZCHIP_READ_BUF(GAR,gar,4)
1266 #define setSUBR(subr) \
1267 WIZCHIP_WRITE_BUF(SUBR, subr,4)
1276 #define getSUBR(subr) \
1277 WIZCHIP_READ_BUF(SUBR, subr, 4)
1285 #define setSHAR(shar) \
1286 WIZCHIP_WRITE_BUF(SHAR, shar, 6)
1294 #define getSHAR(shar) \
1295 WIZCHIP_READ_BUF(SHAR, shar, 6)
1303 #define setSIPR(sipr) \
1304 WIZCHIP_WRITE_BUF(SIPR, sipr, 4)
1312 #define getSIPR(sipr) \
1313 WIZCHIP_READ_BUF(SIPR, sipr, 4)
1321 #define setINTLEVEL(intlevel) {\
1322 WIZCHIP_WRITE(INTLEVEL, (uint8_t)(intlevel >> 8)); \
1323 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(INTLEVEL,1), (uint8_t) intlevel); \
1333 #define getINTLEVEL() \
1334 ((WIZCHIP_READ(INTLEVEL) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(INTLEVEL,1)))
1343 WIZCHIP_WRITE(IR, (ir & 0xF0))
1352 (WIZCHIP_READ(IR) & 0xF0)
1359 #define setIMR(imr) \
1360 WIZCHIP_WRITE(IMR, imr)
1378 #define setSIR(sir) \
1379 WIZCHIP_WRITE(SIR, sir)
1395 #define setSIMR(simr) \
1396 WIZCHIP_WRITE(SIMR, simr)
1413 #define setRTR(rtr) {\
1414 WIZCHIP_WRITE(RTR, (uint8_t)(rtr >> 8)); \
1415 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(RTR,1), (uint8_t) rtr); \
1425 ((WIZCHIP_READ(RTR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(RTR,1)))
1433 #define setRCR(rcr) \
1434 WIZCHIP_WRITE(RCR, rcr)
1453 #define setPTIMER(ptimer) \
1454 WIZCHIP_WRITE(PTIMER, ptimer)
1462 #define getPTIMER() \
1463 WIZCHIP_READ(PTIMER)
1471 #define setPMAGIC(pmagic) \
1472 WIZCHIP_WRITE(PMAGIC, pmagic)
1480 #define getPMAGIC() \
1481 WIZCHIP_READ(PMAGIC)
1489 #define setPHAR(phar) \
1490 WIZCHIP_WRITE_BUF(PHAR, phar, 6)
1498 #define getPHAR(phar) \
1499 WIZCHIP_READ_BUF(PHAR, phar, 6)
1507 #define setPSID(psid) {\
1508 WIZCHIP_WRITE(PSID, (uint8_t)(psid >> 8)); \
1509 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(PSID,1), (uint8_t) psid); \
1520 ((WIZCHIP_READ(PSID) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PSID,1)))
1528 #define setPMRU(pmru) { \
1529 WIZCHIP_WRITE(PMRU, (uint8_t)(pmru>>8)); \
1530 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(PMRU,1), (uint8_t) pmru); \
1540 ((WIZCHIP_READ(PMRU) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PMRU,1)))
1547 #define getUIPR(uipr) \
1548 WIZCHIP_READ_BUF(UIPR,uipr,6)
1555 #define getUPORTR() \
1556 ((WIZCHIP_READ(UPORTR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(UPORTR,1)))
1564 #define setPHYCFGR(phycfgr) \
1565 WIZCHIP_WRITE(PHYCFGR, phycfgr)
1573 #define getPHYCFGR() \
1574 WIZCHIP_READ(PHYCFGR)
1581 #define getVERSIONR() \
1582 WIZCHIP_READ(VERSIONR)
1596 #define setSn_MR(sn, mr) \
1597 WIZCHIP_WRITE(Sn_MR(sn),mr)
1606 #define getSn_MR(sn) \
1607 WIZCHIP_READ(Sn_MR(sn))
1616 #define setSn_CR(sn, cr) \
1617 WIZCHIP_WRITE(Sn_CR(sn), cr)
1626 #define getSn_CR(sn) \
1627 WIZCHIP_READ(Sn_CR(sn))
1636 #define setSn_IR(sn, ir) \
1637 WIZCHIP_WRITE(Sn_IR(sn), (ir & 0x1F))
1646 #define getSn_IR(sn) \
1647 (WIZCHIP_READ(Sn_IR(sn)) & 0x1F)
1656 #define setSn_IMR(sn, imr) \
1657 WIZCHIP_WRITE(Sn_IMR(sn), (imr & 0x1F))
1666 #define getSn_IMR(sn) \
1667 (WIZCHIP_READ(Sn_IMR(sn)) & 0x1F)
1675 #define getSn_SR(sn) \
1676 WIZCHIP_READ(Sn_SR(sn))
1685 #define setSn_PORT(sn, port) { \
1686 WIZCHIP_WRITE(Sn_PORT(sn), (uint8_t)(port >> 8)); \
1687 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1), (uint8_t) port); \
1697 #define getSn_PORT(sn) \
1698 ((WIZCHIP_READ(Sn_PORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1)))
1707 #define setSn_DHAR(sn, dhar) \
1708 WIZCHIP_WRITE_BUF(Sn_DHAR(sn), dhar, 6)
1717 #define getSn_DHAR(sn, dhar) \
1718 WIZCHIP_READ_BUF(Sn_DHAR(sn), dhar, 6)
1727 #define setSn_DIPR(sn, dipr) \
1728 WIZCHIP_WRITE_BUF(Sn_DIPR(sn), dipr, 4)
1737 #define getSn_DIPR(sn, dipr) \
1738 WIZCHIP_READ_BUF(Sn_DIPR(sn), dipr, 4)
1747 #define setSn_DPORT(sn, dport) { \
1748 WIZCHIP_WRITE(Sn_DPORT(sn), (uint8_t) (dport>>8)); \
1749 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1), (uint8_t) dport); \
1759 #define getSn_DPORT(sn) \
1760 ((WIZCHIP_READ(Sn_DPORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1)))
1769 #define setSn_MSSR(sn, mss) { \
1770 WIZCHIP_WRITE(Sn_MSSR(sn), (uint8_t)(mss>>8)); \
1771 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1), (uint8_t) mss); \
1781 #define getSn_MSSR(sn) \
1782 ((WIZCHIP_READ(Sn_MSSR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1)))
1791 #define setSn_TOS(sn, tos) \
1792 WIZCHIP_WRITE(Sn_TOS(sn), tos)
1801 #define getSn_TOS(sn) \
1802 WIZCHIP_READ(Sn_TOS(sn))
1811 #define setSn_TTL(sn, ttl) \
1812 WIZCHIP_WRITE(Sn_TTL(sn), ttl)
1822 #define getSn_TTL(sn) \
1823 WIZCHIP_READ(Sn_TTL(sn))
1833 #define setSn_RXBUF_SIZE(sn, rxbufsize) \
1834 WIZCHIP_WRITE(Sn_RXBUF_SIZE(sn),rxbufsize)
1844 #define getSn_RXBUF_SIZE(sn) \
1845 WIZCHIP_READ(Sn_RXBUF_SIZE(sn))
1854 #define setSn_TXBUF_SIZE(sn, txbufsize) \
1855 WIZCHIP_WRITE(Sn_TXBUF_SIZE(sn), txbufsize)
1864 #define getSn_TXBUF_SIZE(sn) \
1865 WIZCHIP_READ(Sn_TXBUF_SIZE(sn))
1881 #define getSn_TX_RD(sn) \
1882 ((WIZCHIP_READ(Sn_TX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_RD(sn),1)))
1891 #define setSn_TX_WR(sn, txwr) { \
1892 WIZCHIP_WRITE(Sn_TX_WR(sn), (uint8_t)(txwr>>8)); \
1893 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1), (uint8_t) txwr); \
1903 #define getSn_TX_WR(sn) \
1904 ((WIZCHIP_READ(Sn_TX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1)))
1923 #define setSn_RX_RD(sn, rxrd) { \
1924 WIZCHIP_WRITE(Sn_RX_RD(sn), (uint8_t)(rxrd>>8)); \
1925 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1), (uint8_t) rxrd); \
1935 #define getSn_RX_RD(sn) \
1936 ((WIZCHIP_READ(Sn_RX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1)))
1944 #define getSn_RX_WR(sn) \
1945 ((WIZCHIP_READ(Sn_RX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1)))
1955 #define setSn_FRAG(sn, frag) { \
1956 WIZCHIP_WRITE(Sn_FRAG(sn), (uint8_t)(frag >>8)); \
1957 WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1), (uint8_t) frag); \
1967 #define getSn_FRAG(sn) \
1968 ((WIZCHIP_READ(Sn_FRAG(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1)))
1977 #define setSn_KPALVTR(sn, kpalvt) \
1978 WIZCHIP_WRITE(Sn_KPALVTR(sn), kpalvt)
1987 #define getSn_KPALVTR(sn) \
1988 WIZCHIP_READ(Sn_KPALVTR(sn))
2000 #define getSn_RxMAX(sn) \
2001 (getSn_RXBUF_SIZE(sn) << 10)
2009 #define getSn_TxMAX(sn) \
2010 (getSn_TXBUF_SIZE(sn) << 10)
2027 void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
2044 void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len);