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Pin Assignment

Pin Layout#

20170718_w7500p_pinout

Pin Description#

PinNameDescription
1PC_08PWM0/CAP0/GPIO3_8/SCL0/AIN7
2PC_09PWM1/CAP1/GPIO3_9/SDA0/AIN6
3PC_10U_TXD2/GPIO3_10/PWM2/CAP2/AIN5
4PC_11U_RXD2/GPIO3_11/PWM3/CAP3/AIN4
5PC_12AIN3/GPIO3_12/SSEL0
6PC_13AIN2/GPIO3_13/SCLK0
7PC_14AIN1/GPIO14/MISO0
8PC_15AIN0/GPIO3_15/MOSI0
9GNDGROUND
10VDDDigital Power Input: 3.3v
11PC_06GPIO3_6/U_TXD2
12TESTTEST
13REGINRegister Power Input
14LED0LED0 and PHY Address[0]
15DUP/PB_06GPIO2_6/DUP
16GNDGROUND
17LED_3LED3 and PHY Address[3]
18VDD_IODigital Power Input: 3.3v for I/O power supply
19PA_05SSEL0/GPIO1_5/SCL1/PWM2/CAP2
20PA_06SCLK0/GPIO1_6/SDA1/PWM3/CAP3
21PA_07MISO0/GPIO1_7/U_CTS1/PWM4/CAP4
22PA_08MOSI0/GPIO1_8/U_RTS1/PWM5/CAP5
23PA_09SCL0/GPIO1_9/U_TXD1/PWM6/CAP6
24PA_10SDA0/GPIO1_10/U_RXD1/PWM7/CAP7
25VSS_IOGROUND
26RSTNExternal RESET
27PA_00GPIO1_0/PWM6/CAP6
28PA_01GPIO1_1/PWM7/CAP7
29PA_02GPIO1_2/CLKOUT
30PA_03SWCLK/GPIO1_3
31PA_04SWDIO/GPIO1_4
32ISETBandgap Circuit Resister: This pin should be connected to GND via a 6.19Kฮฉ (1%) resistor to define the standard current of the internal citcuit
33GND_1VGROUND
34,35MDI_RN/MDI_RPReceive Input Pair: Differential Pair shared by 100Base-TX and 10Base-T modes
36REGOUTRegister Power Output: This is a regulator power output. A 10uF and 0.1uF should be connected to this pin to filter the power noise
37,38MDI_TN/MDI_TPTransmit Output Pair: Differential pair shared by 100Base-TX and 10Base-T modes. When configured as 100Base-TX, output is an MLT-3 encoded waveform. When configured as 10Base-T, the output is Manchester code
39GNDGROUND
40AVDDAnaloge Power input: 3.3V
41PA_11U_CTS0/GPIO1_11/SSEL1
42PA_12U_RTS0/GPIO1_12/SCLK1
43PA_13U_TXD0/GPIO1_13/MISO1
44PA_14U_RXD0/GPIO1_14/MOSI1
45PB_00SSEL1/GPIO2_0/U_CTS0
46PB_01SCLK1/GPIO2_1/U_RTS0
47PB_02MISO1/GPIO2_2/U_TXD0
48PB_03MOSI1/GPIO2_3/U_RXD0
49GNDGROUND
50XI25MHz Crystal Input: Connects to crystal to provide the 25MHz crystal input. If a 25MHz oscillator is used, connect XI to the oscillator's output. If a 50MHz clock is applied to pin7 TXCLK/50M_CLKI, XI must be connected to GND ot AGND33
51XO25MHz Crystal Output: Connects to crystal to provide the 25MHz output. It must be left open when XI is driven with an external 25MHz oscillator
52BOOTBOOT
53PC_00U_CTS1/GPIO0/PWM0/CAP0
54PC_01U_RTS1/GPIO3_1/PWM1/CAP1
55PC_02U_TXD1/GPIO3_2/PWM2/CAP2
56PC_03U_RXD1/GPIO3_3/PWM3/CAP3
57PC_04SCL1/GPIO3_4/PWM4/CAP4
58PC_05SDA1/GPIO3_5/PWM5/CAP5
61VDDDigital Power Input: 3.3V
62GNDGROUND
63XTAL_INOscillator Input
64XTAL_OUTOscillator Output