48 #define _W5500_IO_BASE_ 0x00000000
50 #define _W5500_SPI_READ_ (0x00 << 2) //< SPI interface Read operation in Control Phase
51 #define _W5500_SPI_WRITE_ (0x01 << 2) //< SPI interface Write operation in Control Phase
53 #define WIZCHIP_CREG_BLOCK 0x00 //< Common register block
54 #define WIZCHIP_SREG_BLOCK(N) (1+4*N) //< Socket N register block
55 #define WIZCHIP_TXBUF_BLOCK(N) (2+4*N) //< Socket N Tx buffer address block
56 #define WIZCHIP_RXBUF_BLOCK(N) (3+4*N) //< Socket N Rx buffer address block
58 #define WIZCHIP_OFFSET_INC(ADDR, N) (ADDR + (N<<8)) //< Increase offset address
115 #define MR (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_CREG_BLOCK << 3))
122 #define GAR (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_CREG_BLOCK << 3))
129 #define SUBR (_W5500_IO_BASE_ + (0x0005 << 8) + (WIZCHIP_CREG_BLOCK << 3))
136 #define SHAR (_W5500_IO_BASE_ + (0x0009 << 8) + (WIZCHIP_CREG_BLOCK << 3))
143 #define SIPR (_W5500_IO_BASE_ + (0x000F << 8) + (WIZCHIP_CREG_BLOCK << 3))
150 #define INTLEVEL (_W5500_IO_BASE_ + (0x0013 << 8) + (WIZCHIP_CREG_BLOCK << 3))
167 #define IR (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_CREG_BLOCK << 3))
185 #define IMR (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_CREG_BLOCK << 3))
193 #define SIR (_W5500_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_CREG_BLOCK << 3))
202 #define SIMR (_W5500_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_CREG_BLOCK << 3))
212 #define RTR (_W5500_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_CREG_BLOCK << 3))
220 #define RCR (_W5500_IO_BASE_ + (0x001B << 8) + (WIZCHIP_CREG_BLOCK << 3))
227 #define PTIMER (_W5500_IO_BASE_ + (0x001C << 8) + (WIZCHIP_CREG_BLOCK << 3))
234 #define PMAGIC (_W5500_IO_BASE_ + (0x001D << 8) + (WIZCHIP_CREG_BLOCK << 3))
241 #define PHAR (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_CREG_BLOCK << 3))
248 #define PSID (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_CREG_BLOCK << 3))
255 #define PMRU (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_CREG_BLOCK << 3))
264 #define UIPR (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_CREG_BLOCK << 3))
273 #define UPORTR (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_CREG_BLOCK << 3))
280 #define PHYCFGR (_W5500_IO_BASE_ + (0x002E << 8) + (WIZCHIP_CREG_BLOCK << 3))
298 #define VERSIONR (_W5500_IO_BASE_ + (0x0039 << 8) + (WIZCHIP_CREG_BLOCK << 3))
332 #define Sn_MR(N) (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
351 #define Sn_CR(N) (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
369 #define Sn_IR(N) (_W5500_IO_BASE_ + (0x0002 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
392 #define Sn_SR(N) (_W5500_IO_BASE_ + (0x0003 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
400 #define Sn_PORT(N) (_W5500_IO_BASE_ + (0x0004 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
408 #define Sn_DHAR(N) (_W5500_IO_BASE_ + (0x0006 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
418 #define Sn_DIPR(N) (_W5500_IO_BASE_ + (0x000C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
428 #define Sn_DPORT(N) (_W5500_IO_BASE_ + (0x0010 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
435 #define Sn_MSSR(N) (_W5500_IO_BASE_ + (0x0012 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
445 #define Sn_TOS(N) (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
452 #define Sn_TTL(N) (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
471 #define Sn_RXBUF_SIZE(N) (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
482 #define Sn_TXBUF_SIZE(N) (_W5500_IO_BASE_ + (0x001F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
493 #define Sn_TX_FSR(N) (_W5500_IO_BASE_ + (0x0020 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
505 #define Sn_TX_RD(N) (_W5500_IO_BASE_ + (0x0022 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
519 #define Sn_TX_WR(N) (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
528 #define Sn_RX_RSR(N) (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
541 #define Sn_RX_RD(N) (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
550 #define Sn_RX_WR(N) (_W5500_IO_BASE_ + (0x002A << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
560 #define Sn_IMR(N) (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
567 #define Sn_FRAG(N) (_W5500_IO_BASE_ + (0x002D << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
580 #define Sn_KPALVTR(N) (_W5500_IO_BASE_ + (0x002F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
619 #define MR_PPPOE 0x08
634 #define IR_CONFLICT 0x80
641 #define IR_UNREACH 0x40
647 #define IR_PPPoE 0x20
657 #define PHYCFGR_RST ~(1<<7) //< For PHY reset, must operate AND mask.
658 #define PHYCFGR_OPMD (1<<6) // Configre PHY with OPMDC value
659 #define PHYCFGR_OPMDC_ALLA (7<<3)
660 #define PHYCFGR_OPMDC_PDOWN (6<<3)
661 #define PHYCFGR_OPMDC_NA (5<<3)
662 #define PHYCFGR_OPMDC_100FA (4<<3)
663 #define PHYCFGR_OPMDC_100F (3<<3)
664 #define PHYCFGR_OPMDC_100H (2<<3)
665 #define PHYCFGR_OPMDC_10F (1<<3)
666 #define PHYCFGR_OPMDC_10H (0<<3)
667 #define PHYCFGR_DPX_FULL (1<<2)
668 #define PHYCFGR_DPX_HALF (0<<2)
669 #define PHYCFGR_SPD_100 (1<<1)
670 #define PHYCFGR_SPD_10 (0<<1)
671 #define PHYCFGR_LNK_ON (1<<0)
672 #define PHYCFGR_LNK_OFF (0<<0)
712 #define Sn_MR_MULTI 0x80
721 #define Sn_MR_BCASTB 0x40
731 #define Sn_MR_ND 0x20
739 #define Sn_MR_UCASTB 0x10
746 #define Sn_MR_MACRAW 0x04
754 #define Sn_MR_UDP 0x02
760 #define Sn_MR_TCP 0x01
766 #define Sn_MR_CLOSE 0x00
779 #define Sn_MR_MFEN Sn_MR_MULTI
788 #define Sn_MR_MMB Sn_MR_ND
796 #define Sn_MR_MIP6B Sn_MR_UCASTB
805 #define Sn_MR_MC Sn_MR_ND
811 #define SOCK_STREAM Sn_MR_TCP
816 #define SOCK_DGRAM Sn_MR_UDP
832 #define Sn_CR_OPEN 0x01
843 #define Sn_CR_LISTEN 0x02
855 #define Sn_CR_CONNECT 0x04
868 #define Sn_CR_DISCON 0x08
874 #define Sn_CR_CLOSE 0x10
882 #define Sn_CR_SEND 0x20
892 #define Sn_CR_SEND_MAC 0x21
900 #define Sn_CR_SEND_KEEP 0x22
908 #define Sn_CR_RECV 0x40
915 #define Sn_IR_SENDOK 0x10
921 #define Sn_IR_TIMEOUT 0x08
927 #define Sn_IR_RECV 0x04
933 #define Sn_IR_DISCON 0x02
939 #define Sn_IR_CON 0x01
947 #define SOCK_CLOSED 0x00
955 #define SOCK_INIT 0x13
963 #define SOCK_LISTEN 0x14
972 #define SOCK_SYNSENT 0x15
980 #define SOCK_SYNRECV 0x16
989 #define SOCK_ESTABLISHED 0x17
997 #define SOCK_FIN_WAIT 0x18
1005 #define SOCK_CLOSING 0x1A
1013 #define SOCK_TIME_WAIT 0x1B
1021 #define SOCK_CLOSE_WAIT 0x1C
1028 #define SOCK_LAST_ACK 0x1D
1036 #define SOCK_UDP 0x22
1046 #define SOCK_MACRAW 0x42
1051 #define IPPROTO_IP 0 //< Dummy for IP
1052 #define IPPROTO_ICMP 1 //< Control message protocol
1053 #define IPPROTO_IGMP 2 //< Internet group management protocol
1054 #define IPPROTO_GGP 3 //< Gateway^2 (deprecated)
1055 #define IPPROTO_TCP 6 //< TCP
1056 #define IPPROTO_PUP 12 //< PUP
1057 #define IPPROTO_UDP 17 //< UDP
1058 #define IPPROTO_IDP 22 //< XNS idp
1059 #define IPPROTO_ND 77 //< UNOFFICIAL net disk protocol
1060 #define IPPROTO_RAW 255 //< Raw IP packet
1195 void setMR(uint8_t mr);
1203 uint8_t
getMR(
void);
1211 void setGAR(uint8_t* gar);
1219 void getGAR(uint8_t* gar);
1291 void setIR(uint8_t ir);
1299 uint8_t
getIR(
void);
1307 void setIMR(uint8_t imr);
1323 void setSIR(uint8_t sir);
1355 void setRTR(uint16_t rtr);
1371 void setRCR(uint8_t rcr);
1510 void setSn_MR(uint8_t sn, uint8_t mr);
1527 void setSn_CR(uint8_t sn, uint8_t cr);
1544 void setSn_IR(uint8_t sn, uint8_t ir);
1561 void setSn_IMR(uint8_t sn, uint8_t imr);
1672 void setSn_TOS(uint8_t sn, uint8_t tos);
1689 void setSn_TTL(uint8_t sn, uint8_t ttl);
1859 void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
1876 void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len);