ioLibrary for Cortex M series
Macros
Common register

Common register group
It set the basic for the networking
It set the configuration such as interrupt, network information, ICMP, etc. More...

Collaboration diagram for Common register:

Macros

#define MR   (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_CREG_BLOCK << 3))
 Mode Register address(R/W)
MR is used for S/W reset, ping block mode, PPPoE mode and etc. More...
 
#define GAR   (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_CREG_BLOCK << 3))
 Gateway IP Register address(R/W) More...
 
#define SUBR   (_W5500_IO_BASE_ + (0x0005 << 8) + (WIZCHIP_CREG_BLOCK << 3))
 Subnet mask Register address(R/W) More...
 
#define SHAR   (_W5500_IO_BASE_ + (0x0009 << 8) + (WIZCHIP_CREG_BLOCK << 3))
 Source MAC Register address(R/W) More...
 
#define SIPR   (_W5500_IO_BASE_ + (0x000F << 8) + (WIZCHIP_CREG_BLOCK << 3))
 Source IP Register address(R/W) More...
 
#define INTLEVEL   (_W5500_IO_BASE_ + (0x0013 << 8) + (WIZCHIP_CREG_BLOCK << 3))
 Set Interrupt low level timer register address(R/W) More...
 
#define IR   (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_CREG_BLOCK << 3))
 Interrupt Register(R/W) More...
 
#define IMR   (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_CREG_BLOCK << 3))
 Interrupt mask register(R/W) More...
 
#define SIR   (_W5500_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_CREG_BLOCK << 3))
 Socket Interrupt Register(R/W) More...
 
#define SIMR   (_W5500_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_CREG_BLOCK << 3))
 Socket Interrupt Mask Register(R/W) More...
 
#define RTR   (_W5500_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_CREG_BLOCK << 3))
 Timeout register address( 1 is 100us )(R/W) More...
 
#define RCR   (_W5500_IO_BASE_ + (0x001B << 8) + (WIZCHIP_CREG_BLOCK << 3))
 Retry count register(R/W) More...
 
#define PTIMER   (_W5500_IO_BASE_ + (0x001C << 8) + (WIZCHIP_CREG_BLOCK << 3))
 PPP LCP Request Timer register in PPPoE mode(R/W) More...
 
#define PMAGIC   (_W5500_IO_BASE_ + (0x001D << 8) + (WIZCHIP_CREG_BLOCK << 3))
 PPP LCP Magic number register in PPPoE mode(R/W) More...
 
#define PHAR   (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_CREG_BLOCK << 3))
 PPP Destination MAC Register address(R/W) More...
 
#define PSID   (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_CREG_BLOCK << 3))
 PPP Session Identification Register(R/W) More...
 
#define PMRU   (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_CREG_BLOCK << 3))
 PPP Maximum Segment Size(MSS) register(R/W) More...
 
#define UIPR   (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_CREG_BLOCK << 3))
 Unreachable IP register address in UDP mode(R) More...
 
#define UPORTR   (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_CREG_BLOCK << 3))
 Unreachable Port register address in UDP mode(R) More...
 
#define PHYCFGR   (_W5500_IO_BASE_ + (0x002E << 8) + (WIZCHIP_CREG_BLOCK << 3))
 PHY Status Register(R/W) More...
 
#define VERSIONR   (_W5500_IO_BASE_ + (0x0039 << 8) + (WIZCHIP_CREG_BLOCK << 3))
 chip version register address(R) More...
 

Detailed Description

Common register group
It set the basic for the networking
It set the configuration such as interrupt, network information, ICMP, etc.

See Also
MR : Mode register.
GAR, SUBR, SHAR, SIPR
INTLEVEL, IR, IMR, SIR, SIMR : Interrupt.
RTR, RCR : Data retransmission.
PTIMER, PMAGIC, PHAR, PSID, PMRU : PPPoE.
UIPR, UPORT : ICMP message.
PHYCFGR, VERSIONR : etc.

Macro Definition Documentation

#define MR   (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Mode Register address(R/W)
MR is used for S/W reset, ping block mode, PPPoE mode and etc.

Each bit of MR defined as follows.

7 6 5 4 3 2 1 0
RST Reserved WOL PB PPPoE Reserved FARP Reserved

Definition at line 115 of file w5500.h.

Referenced by getMR(), and setMR().

#define GAR   (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Gateway IP Register address(R/W)

GAR configures the default gateway address.

Definition at line 122 of file w5500.h.

Referenced by getGAR(), and setGAR().

#define SUBR   (_W5500_IO_BASE_ + (0x0005 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Subnet mask Register address(R/W)

SUBR configures the subnet mask address.

Definition at line 129 of file w5500.h.

Referenced by getSUBR(), and setSUBR().

#define SHAR   (_W5500_IO_BASE_ + (0x0009 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Source MAC Register address(R/W)

SHAR configures the source hardware address.

Definition at line 136 of file w5500.h.

Referenced by getSHAR(), and setSHAR().

#define SIPR   (_W5500_IO_BASE_ + (0x000F << 8) + (WIZCHIP_CREG_BLOCK << 3))

Source IP Register address(R/W)

SIPR configures the source IP address.

Definition at line 143 of file w5500.h.

Referenced by getSIPR(), and setSIPR().

#define INTLEVEL   (_W5500_IO_BASE_ + (0x0013 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Set Interrupt low level timer register address(R/W)

INTLEVEL configures the Interrupt Assert Time.

Definition at line 150 of file w5500.h.

Referenced by getINTLEVEL(), and setINTLEVEL().

#define IR   (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Interrupt Register(R/W)

IR indicates the interrupt status. Each bit of IR will be still until the bit will be written to by the host. If IR is not equal to x00 INTn PIN is asserted to low until it is x00

Each bit of IR defined as follows.

7 6 5 4 3 2 1 0
CONFLICT UNREACH PPPoE MP Reserved Reserved Reserved Reserved

Definition at line 167 of file w5500.h.

Referenced by getIR(), and setIR().

#define IMR   (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Interrupt mask register(R/W)

IMR is used to mask interrupts. Each bit of IMR corresponds to each bit of IR. When a bit of IMR is and the corresponding bit of IR is an interrupt will be issued. In other words, if a bit of IMR is an interrupt will not be issued even if the corresponding bit of IR is

Each bit of IMR defined as the following.

7 6 5 4 3 2 1 0
IM_IR7 IM_IR6 IM_IR5 IM_IR4 Reserved Reserved Reserved Reserved
  • IM_IR7 : IP Conflict Interrupt Mask
  • IM_IR6 : Destination unreachable Interrupt Mask
  • IM_IR5 : PPPoE Close Interrupt Mask
  • IM_IR4 : Magic Packet Interrupt Mask

Definition at line 185 of file w5500.h.

Referenced by getIMR(), and setIMR().

#define SIR   (_W5500_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Socket Interrupt Register(R/W)

SIR indicates the interrupt status of Socket.
Each bit of SIR be still until Sn_IR is cleared by the host.
If Sn_IR is not equal to x00 the n-th bit of SIR is and INTn PIN is asserted until SIR is x00

Definition at line 193 of file w5500.h.

Referenced by getSIR(), and setSIR().

#define SIMR   (_W5500_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Socket Interrupt Mask Register(R/W)

Each bit of SIMR corresponds to each bit of SIR. When a bit of SIMR is and the corresponding bit of SIR is Interrupt will be issued. In other words, if a bit of SIMR is an interrupt will be not issued even if the corresponding bit of SIR is

Definition at line 202 of file w5500.h.

Referenced by getSIMR(), and setSIMR().

#define RTR   (_W5500_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Timeout register address( 1 is 100us )(R/W)

RTR configures the retransmission timeout period. The unit of timeout period is 100us and the default of RTR is x07D0or 000 And so the default timeout period is 200ms(100us X 2000). During the time configured by RTR, W5500 waits for the peer response to the packet that is transmitted by Sn_CR (CONNECT, DISCON, CLOSE, SEND, SEND_MAC, SEND_KEEP command). If the peer does not respond within the RTR time, W5500 retransmits the packet or issues timeout.

Definition at line 212 of file w5500.h.

Referenced by getRTR(), and setRTR().

#define RCR   (_W5500_IO_BASE_ + (0x001B << 8) + (WIZCHIP_CREG_BLOCK << 3))

Retry count register(R/W)

RCR configures the number of time of retransmission. When retransmission occurs as many as ref RCR+1 Timeout interrupt is issued (Sn_IR[TIMEOUT] = .

Definition at line 220 of file w5500.h.

Referenced by getRCR(), and setRCR().

#define PTIMER   (_W5500_IO_BASE_ + (0x001C << 8) + (WIZCHIP_CREG_BLOCK << 3))

PPP LCP Request Timer register in PPPoE mode(R/W)

PTIMER configures the time for sending LCP echo request. The unit of time is 25ms.

Definition at line 227 of file w5500.h.

Referenced by getPTIMER(), and setPTIMER().

#define PMAGIC   (_W5500_IO_BASE_ + (0x001D << 8) + (WIZCHIP_CREG_BLOCK << 3))

PPP LCP Magic number register in PPPoE mode(R/W)

PMAGIC configures the 4bytes magic number to be used in LCP negotiation.

Definition at line 234 of file w5500.h.

Referenced by getPMAGIC(), and setPMAGIC().

#define PHAR   (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_CREG_BLOCK << 3))

PPP Destination MAC Register address(R/W)

PHAR configures the PPPoE server hardware address that is acquired during PPPoE connection process.

Definition at line 241 of file w5500.h.

Referenced by getPHAR(), and setPHAR().

#define PSID   (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_CREG_BLOCK << 3))

PPP Session Identification Register(R/W)

PSID configures the PPPoE sever session ID acquired during PPPoE connection process.

Definition at line 248 of file w5500.h.

Referenced by getPSID(), and setPSID().

#define PMRU   (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_CREG_BLOCK << 3))

PPP Maximum Segment Size(MSS) register(R/W)

PMRU configures the maximum receive unit of PPPoE.

Definition at line 255 of file w5500.h.

Referenced by getPMRU(), and setPMRU().

#define UIPR   (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_CREG_BLOCK << 3))

Unreachable IP register address in UDP mode(R)

W5500 receives an ICMP packet(Destination port unreachable) when data is sent to a port number which socket is not open and UNREACH bit of IR becomes and UIPR & UPORT indicates the destination IP address & port number respectively.

Definition at line 264 of file w5500.h.

Referenced by getUIPR().

#define UPORTR   (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_CREG_BLOCK << 3))

Unreachable Port register address in UDP mode(R)

W5500 receives an ICMP packet(Destination port unreachable) when data is sent to a port number which socket is not open and UNREACH bit of IR becomes and UIPR & UPORT indicates the destination IP address & port number respectively.

Definition at line 273 of file w5500.h.

Referenced by getUPORTR().

#define PHYCFGR   (_W5500_IO_BASE_ + (0x002E << 8) + (WIZCHIP_CREG_BLOCK << 3))

PHY Status Register(R/W)

PHYCFGR configures PHY operation mode and resets PHY. In addition, PHYCFGR indicates the status of PHY such as duplex, Speed, Link.

Definition at line 280 of file w5500.h.

Referenced by getPHYCFGR(), and setPHYCFGR().

#define VERSIONR   (_W5500_IO_BASE_ + (0x0039 << 8) + (WIZCHIP_CREG_BLOCK << 3))

chip version register address(R)

VERSIONR always indicates the W5500 version as 0x04.

Definition at line 298 of file w5500.h.

Referenced by getVERSIONR().