15 #define USART1_RX_INTERRUPT VAL_DISABLE//VAL_DISABLE//VAL_ENABLE
16 #define USART2_RX_INTERRUPT VAL_DISABLE//VAL_DISABLE//VAL_ENABLE
17 #define SYSTICK_HZ 1000
28 #if (USART1_RX_INTERRUPT == VAL_ENABLE)
29 #define U0RX_BUF_SIZE 16
34 if(UARTIntStatus(xUART0_BASE, xUART_INT_RX) != RESET) {
35 UARTIntClear(xUART0_BASE, xUART_INT_RX);
40 UARTCharPut(xUART0_BASE, (uint8_t)
'@');
50 #if (USART2_RX_INTERRUPT == VAL_ENABLE)
51 #define U1RX_BUF_SIZE 16
56 if(UARTIntStatus(xUART1_BASE, xUART_INT_RX) != RESET) {
57 UARTIntClear(xUART1_BASE, xUART_INT_RX);
62 UARTCharPut(xUART1_BASE, (uint8_t)
'@');
75 uint8_t tx_size[8]={2, 2, 2, 2, 2, 2, 2, 2};
76 uint8_t rx_size[8]={2, 2, 2, 2, 2, 2, 2, 2};
78 xSysCtlClockSet(12000000, xSYSCTL_OSC_MAIN | xSYSCTL_XTAL_12MHZ);
80 xSysCtlDelay(44000000);
81 xSysTickPeriodSet(xSysCtlClockGet()/1000);
84 xSysCtlPeripheralEnable(xSYSCTL_PERIPH_GPIOA );
85 xSysCtlPeripheralEnable(xSYSCTL_PERIPH_GPIOB );
87 xSysCtlPeripheralReset(xSYSCTL_PERIPH_UART0);
88 xSysCtlPeripheralEnable(xSYSCTL_PERIPH_UART0);
94 xSPinTypeUART(UART0TX, PA2);
95 xSPinTypeUART(UART0RX, PA3);
98 xUARTConfigSet(xUART0_BASE, 115200, (UART_CONFIG_WLEN_8 |
99 UART_CONFIG_STOP_ONE |
100 UART_CONFIG_PAR_NONE));
105 xUARTConfigSet(xUART0_BASE, up->
baudrate, (UART_CONFIG_WLEN_8 |
106 UART_CONFIG_STOP_ONE |
107 UART_CONFIG_PAR_NONE));
109 #if (USART1_RX_INTERRUPT == VAL_ENABLE)
112 #if (USART2_RX_INTERRUPT == VAL_ENABLE)
116 xUARTEnable(xUART0_BASE, (UART_BLOCK_UART | UART_BLOCK_TX | UART_BLOCK_RX));
120 ERR(
"ERR: wizpf_spi_init fail");
127 #if (_WIZCHIP_IO_MODE_== _WIZCHIP_IO_MODE_SPI_FDM_)
137 ERR(
"ERR: WIZCHIP fail to initialized!!!");
145 #if (USART1_RX_INTERRUPT == VAL_ENABLE)
146 xUARTIntEnable(xUART0_BASE,xUART_INT_RX);
160 xGPIOPinWrite( WIZ_RESET_PORT, WIZ_RESET_PIN, 0);
162 xGPIOPinWrite( WIZ_RESET_PORT, WIZ_RESET_PIN, 1);
169 register uint8_t i, j;
171 for(i=0; i<time_us; i++) {
186 for(i=0; i<time_ms; i++) {
200 while(
msTicks - curTicks < tick);
237 xSysCtlPeripheralReset(xSYSCTL_PERIPH_SPI0);
238 xSysCtlPeripheralEnable(xSYSCTL_PERIPH_SPI0);
239 xGPIODirModeSet(xGPIO_PORTA_BASE, xGPIO_PIN_4, xGPIO_DIR_MODE_OUT);
244 xSPIConfigSet(xSPI0_BASE, 18000000, xSPI_MOTO_FORMAT_MODE_0 | xSPI_MODE_MASTER | xSPI_MSB_FIRST | xSPI_DATA_WIDTH8);
246 xSPISSSet(xSPI0_BASE, SPI_SS_SOFTWARE, xSPI_SS_NONE);
248 xSPIEnable(xSPI0_BASE);
251 xSysCtlPeripheralReset(xSYSCTL_PERIPH_SPI1);
252 xSysCtlPeripheralEnable(xSYSCTL_PERIPH_SPI1);
253 xGPIODirModeSet(xGPIO_PORTA_BASE, xGPIO_PIN_4, xGPIO_DIR_MODE_OUT);
260 xSPIConfigSet(xSPI1_BASE, 18000000, xSPI_MOTO_FORMAT_MODE_0 | xSPI_MODE_MASTER | xSPI_MSB_FIRST | xSPI_DATA_WIDTH8);
261 xSPISSSet(xSPI1_BASE, SPI_SS_SOFTWARE, xSPI_SS_NONE);
263 xSPIEnable(xSPI1_BASE);
277 uint32_t GPIO_Port = 0;
278 uint32_t GPIO_Pin = 0;
297 xGPIOPinWrite( GPIO_Port, GPIO_Pin, 0);
298 }
else if(action ==
VAL_ON) {
299 xGPIOPinWrite( GPIO_Port, GPIO_Pin, 1);
302 xGPIOPinWrite( GPIO_Port, GPIO_Pin, 0);
304 xGPIOPinWrite( GPIO_Port, GPIO_Pin, 1);
312 uint32_t GPIO_Port = 0;
313 uint32_t GPIO_Pin = 0;
328 return (int8_t)xGPIOPinRead(GPIO_Port,GPIO_Pin);
338 for(i=0; i<repeat; i++) {
351 if(!xIntMasterEnable())
353 ERR(
"Fail to enter critical section for WIZCHIP\r\n");
359 if(!xIntMasterDisable())
361 ERR(
"Fail to exit critical section for WIZCHIP\r\n");
378 xSPISingleDataReadWrite(xSPI0_BASE,wb);
383 return xSPISingleDataReadWrite(xSPI0_BASE,0xFF);
392 else if(usart ==
WIZ_USART2) USARTx = xUART1_BASE;
395 UARTCharPut(USARTx, (uint8_t)ch);
401 #if (USART1_RX_INTERRUPT == VAL_ENABLE)
414 #if (USART2_RX_INTERRUPT == VAL_ENABLE)
427 #if (USART1_RX_INTERRUPT == VAL_DISABLE) || (USART2_RX_INTERRUPT == VAL_DISABLE)
432 else if(usart ==
WIZ_USART2) USARTx = xUART1_BASE;
434 return UARTCharGet(USARTx);
443 #if (USART1_RX_INTERRUPT == VAL_ENABLE)
456 #if (USART2_RX_INTERRUPT == VAL_ENABLE)
469 #if (USART1_RX_INTERRUPT == VAL_DISABLE) || (USART2_RX_INTERRUPT == VAL_DISABLE)
474 else if(usart ==
WIZ_USART2) USARTx = xUART1_BASE;
476 return UARTCharGetNonBlocking(USARTx);