ioLibrary for Cortex M series
w5500.h
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1 //*****************************************************************************
2 //
39 //
40 //*****************************************************************************
41 
42 #ifndef _W5500_H_
43 #define _W5500_H_
44 
45 #include <stdint.h>
46 #include "Ethernet/wizchip_conf.h"
47 
48 #define _W5500_IO_BASE_ 0x00000000
49 
50 #define _W5500_SPI_READ_ (0x00 << 2) //< SPI interface Read operation in Control Phase
51 #define _W5500_SPI_WRITE_ (0x01 << 2) //< SPI interface Write operation in Control Phase
52 
53 #define WIZCHIP_CREG_BLOCK 0x00 //< Common register block
54 #define WIZCHIP_SREG_BLOCK(N) (1+4*N) //< Socket N register block
55 #define WIZCHIP_TXBUF_BLOCK(N) (2+4*N) //< Socket N Tx buffer address block
56 #define WIZCHIP_RXBUF_BLOCK(N) (3+4*N) //< Socket N Rx buffer address block
57 
58 #define WIZCHIP_OFFSET_INC(ADDR, N) (ADDR + (N<<8)) //< Increase offset address
59 
60 
61 
63 
99 //----------------------------- W5500 Common Registers IOMAP -----------------------------
115 #define MR (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_CREG_BLOCK << 3))
116 
122 #define GAR (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_CREG_BLOCK << 3))
123 
129 #define SUBR (_W5500_IO_BASE_ + (0x0005 << 8) + (WIZCHIP_CREG_BLOCK << 3))
130 
136 #define SHAR (_W5500_IO_BASE_ + (0x0009 << 8) + (WIZCHIP_CREG_BLOCK << 3))
137 
143 #define SIPR (_W5500_IO_BASE_ + (0x000F << 8) + (WIZCHIP_CREG_BLOCK << 3))
144 
150 #define INTLEVEL (_W5500_IO_BASE_ + (0x0013 << 8) + (WIZCHIP_CREG_BLOCK << 3))
151 
167 #define IR (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_CREG_BLOCK << 3))
168 
185 #define IMR (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_CREG_BLOCK << 3))
186 
193 #define SIR (_W5500_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_CREG_BLOCK << 3))
194 
202 #define SIMR (_W5500_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_CREG_BLOCK << 3))
203 
212 #define RTR (_W5500_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_CREG_BLOCK << 3))
213 
220 #define RCR (_W5500_IO_BASE_ + (0x001B << 8) + (WIZCHIP_CREG_BLOCK << 3))
221 
227 #define PTIMER (_W5500_IO_BASE_ + (0x001C << 8) + (WIZCHIP_CREG_BLOCK << 3))
228 
234 #define PMAGIC (_W5500_IO_BASE_ + (0x001D << 8) + (WIZCHIP_CREG_BLOCK << 3))
235 
241 #define PHAR (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_CREG_BLOCK << 3))
242 
248 #define PSID (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_CREG_BLOCK << 3))
249 
255 #define PMRU (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_CREG_BLOCK << 3))
256 
264 #define UIPR (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_CREG_BLOCK << 3))
265 
273 #define UPORTR (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_CREG_BLOCK << 3))
274 
280 #define PHYCFGR (_W5500_IO_BASE_ + (0x002E << 8) + (WIZCHIP_CREG_BLOCK << 3))
281 
282 // Reserved (_W5500_IO_BASE_ + (0x002F << 8) + (WIZCHIP_CREG_BLOCK << 3))
283 // Reserved (_W5500_IO_BASE_ + (0x0030 << 8) + (WIZCHIP_CREG_BLOCK << 3))
284 // Reserved (_W5500_IO_BASE_ + (0x0031 << 8) + (WIZCHIP_CREG_BLOCK << 3))
285 // Reserved (_W5500_IO_BASE_ + (0x0032 << 8) + (WIZCHIP_CREG_BLOCK << 3))
286 // Reserved (_W5500_IO_BASE_ + (0x0033 << 8) + (WIZCHIP_CREG_BLOCK << 3))
287 // Reserved (_W5500_IO_BASE_ + (0x0034 << 8) + (WIZCHIP_CREG_BLOCK << 3))
288 // Reserved (_W5500_IO_BASE_ + (0x0035 << 8) + (WIZCHIP_CREG_BLOCK << 3))
289 // Reserved (_W5500_IO_BASE_ + (0x0036 << 8) + (WIZCHIP_CREG_BLOCK << 3))
290 // Reserved (_W5500_IO_BASE_ + (0x0037 << 8) + (WIZCHIP_CREG_BLOCK << 3))
291 // Reserved (_W5500_IO_BASE_ + (0x0038 << 8) + (WIZCHIP_CREG_BLOCK << 3))
292 
298 #define VERSIONR (_W5500_IO_BASE_ + (0x0039 << 8) + (WIZCHIP_CREG_BLOCK << 3))
299 
300 
301 //----------------------------- W5500 Socket Registers IOMAP -----------------------------
332 #define Sn_MR(N) (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
333 
351 #define Sn_CR(N) (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
352 
369 #define Sn_IR(N) (_W5500_IO_BASE_ + (0x0002 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
370 
392 #define Sn_SR(N) (_W5500_IO_BASE_ + (0x0003 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
393 
400 #define Sn_PORT(N) (_W5500_IO_BASE_ + (0x0004 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
401 
408 #define Sn_DHAR(N) (_W5500_IO_BASE_ + (0x0006 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
409 
418 #define Sn_DIPR(N) (_W5500_IO_BASE_ + (0x000C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
419 
428 #define Sn_DPORT(N) (_W5500_IO_BASE_ + (0x0010 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
429 
435 #define Sn_MSSR(N) (_W5500_IO_BASE_ + (0x0012 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
436 
437 // Reserved (_W5500_IO_BASE_ + (0x0014 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
438 
445 #define Sn_TOS(N) (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
446 
452 #define Sn_TTL(N) (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
453 // Reserved (_W5500_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
454 // Reserved (_W5500_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
455 // Reserved (_W5500_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
456 // Reserved (_W5500_IO_BASE_ + (0x001A << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
457 // Reserved (_W5500_IO_BASE_ + (0x001B << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
458 // Reserved (_W5500_IO_BASE_ + (0x001C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
459 // Reserved (_W5500_IO_BASE_ + (0x001D << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
460 
471 #define Sn_RXBUF_SIZE(N) (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
472 
482 #define Sn_TXBUF_SIZE(N) (_W5500_IO_BASE_ + (0x001F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
483 
493 #define Sn_TX_FSR(N) (_W5500_IO_BASE_ + (0x0020 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
494 
505 #define Sn_TX_RD(N) (_W5500_IO_BASE_ + (0x0022 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
506 
519 #define Sn_TX_WR(N) (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
520 
528 #define Sn_RX_RSR(N) (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
529 
541 #define Sn_RX_RD(N) (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
542 
550 #define Sn_RX_WR(N) (_W5500_IO_BASE_ + (0x002A << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
551 
560 #define Sn_IMR(N) (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
561 
567 #define Sn_FRAG(N) (_W5500_IO_BASE_ + (0x002D << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
568 
580 #define Sn_KPALVTR(N) (_W5500_IO_BASE_ + (0x002F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
581 
582 //#define Sn_TSR(N) (_W5500_IO_BASE_ + (0x0030 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
583 
584 
585 //----------------------------- W5500 Register values -----------------------------
586 
587 /* MODE register values */
592 #define MR_RST 0x80
593 
603 #define MR_WOL 0x20
604 
611 #define MR_PB 0x10
612 
619 #define MR_PPPOE 0x08
620 
627 #define MR_FARP 0x02
628 
629 /* IR register values */
634 #define IR_CONFLICT 0x80
635 
641 #define IR_UNREACH 0x40
642 
647 #define IR_PPPoE 0x20
648 
653 #define IR_MP 0x10
654 
655 
656 /* PHYCFGR register value */
657 #define PHYCFGR_RST ~(1<<7) //< For PHY reset, must operate AND mask.
658 #define PHYCFGR_OPMD (1<<6) // Configre PHY with OPMDC value
659 #define PHYCFGR_OPMDC_ALLA (7<<3)
660 #define PHYCFGR_OPMDC_PDOWN (6<<3)
661 #define PHYCFGR_OPMDC_NA (5<<3)
662 #define PHYCFGR_OPMDC_100FA (4<<3)
663 #define PHYCFGR_OPMDC_100F (3<<3)
664 #define PHYCFGR_OPMDC_100H (2<<3)
665 #define PHYCFGR_OPMDC_10F (1<<3)
666 #define PHYCFGR_OPMDC_10H (0<<3)
667 #define PHYCFGR_DPX_FULL (1<<2)
668 #define PHYCFGR_DPX_HALF (0<<2)
669 #define PHYCFGR_SPD_100 (1<<1)
670 #define PHYCFGR_SPD_10 (0<<1)
671 #define PHYCFGR_LNK_ON (1<<0)
672 #define PHYCFGR_LNK_OFF (0<<0)
673 
674 /* IMR register values */
680 #define IM_IR7 0x80
681 
687 #define IM_IR6 0x40
688 
694 #define IM_IR5 0x20
695 
701 #define IM_IR4 0x10
702 
703 /* Sn_MR Default values */
712 #define Sn_MR_MULTI 0x80
713 
721 #define Sn_MR_BCASTB 0x40
722 
731 #define Sn_MR_ND 0x20
732 
739 #define Sn_MR_UCASTB 0x10
740 
746 #define Sn_MR_MACRAW 0x04
747 
748 //#define Sn_MR_IPRAW 0x03 /**< IP LAYER RAW SOCK */
749 
754 #define Sn_MR_UDP 0x02
755 
760 #define Sn_MR_TCP 0x01
761 
766 #define Sn_MR_CLOSE 0x00
767 
768 /* Sn_MR values used with Sn_MR_MACRAW */
779 #define Sn_MR_MFEN Sn_MR_MULTI
780 
788 #define Sn_MR_MMB Sn_MR_ND
789 
796 #define Sn_MR_MIP6B Sn_MR_UCASTB
797 
798 /* Sn_MR value used with Sn_MR_UDP & Sn_MR_MULTI */
805 #define Sn_MR_MC Sn_MR_ND
806 
807 /* Sn_MR alternate values */
811 #define SOCK_STREAM Sn_MR_TCP
812 
816 #define SOCK_DGRAM Sn_MR_UDP
817 
818 
819 /* Sn_CR values */
832 #define Sn_CR_OPEN 0x01
833 
843 #define Sn_CR_LISTEN 0x02
844 
855 #define Sn_CR_CONNECT 0x04
856 
868 #define Sn_CR_DISCON 0x08
869 
874 #define Sn_CR_CLOSE 0x10
875 
882 #define Sn_CR_SEND 0x20
883 
892 #define Sn_CR_SEND_MAC 0x21
893 
900 #define Sn_CR_SEND_KEEP 0x22
901 
908 #define Sn_CR_RECV 0x40
909 
910 /* Sn_IR values */
915 #define Sn_IR_SENDOK 0x10
916 
921 #define Sn_IR_TIMEOUT 0x08
922 
927 #define Sn_IR_RECV 0x04
928 
933 #define Sn_IR_DISCON 0x02
934 
939 #define Sn_IR_CON 0x01
940 
941 /* Sn_SR values */
947 #define SOCK_CLOSED 0x00
948 
955 #define SOCK_INIT 0x13
956 
963 #define SOCK_LISTEN 0x14
964 
972 #define SOCK_SYNSENT 0x15
973 
980 #define SOCK_SYNRECV 0x16
981 
989 #define SOCK_ESTABLISHED 0x17
990 
997 #define SOCK_FIN_WAIT 0x18
998 
1005 #define SOCK_CLOSING 0x1A
1006 
1013 #define SOCK_TIME_WAIT 0x1B
1014 
1021 #define SOCK_CLOSE_WAIT 0x1C
1022 
1028 #define SOCK_LAST_ACK 0x1D
1029 
1036 #define SOCK_UDP 0x22
1037 
1038 //#define SOCK_IPRAW 0x32 /**< IP raw mode socket */
1039 
1046 #define SOCK_MACRAW 0x42
1047 
1048 //#define SOCK_PPPOE 0x5F
1049 
1050 /* IP PROTOCOL */
1051 #define IPPROTO_IP 0 //< Dummy for IP
1052 #define IPPROTO_ICMP 1 //< Control message protocol
1053 #define IPPROTO_IGMP 2 //< Internet group management protocol
1054 #define IPPROTO_GGP 3 //< Gateway^2 (deprecated)
1055 #define IPPROTO_TCP 6 //< TCP
1056 #define IPPROTO_PUP 12 //< PUP
1057 #define IPPROTO_UDP 17 //< UDP
1058 #define IPPROTO_IDP 22 //< XNS idp
1059 #define IPPROTO_ND 77 //< UNOFFICIAL net disk protocol
1060 #define IPPROTO_RAW 255 //< Raw IP packet
1061 
1062 
1074 void WIZCHIP_CRITICAL_ENTER(void);
1075 
1087 void WIZCHIP_CRITICAL_EXIT(void);
1088 
1147 // Basic I/O Function //
1150 
1157 uint8_t WIZCHIP_READ (uint32_t AddrSel);
1158 
1166 void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb );
1167 
1175 void WIZCHIP_READ_BUF (uint32_t AddrSel, uint8_t* pBuf, uint16_t len);
1176 
1184 void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len);
1185 
1187 // Common Register I/O function //
1189 
1195 void setMR(uint8_t mr);
1196 
1203 uint8_t getMR(void);
1204 
1211 void setGAR(uint8_t* gar);
1212 
1219 void getGAR(uint8_t* gar);
1220 
1227 void setSUBR(uint8_t* subr);
1228 
1235 void getSUBR(uint8_t* subr);
1236 
1243 void setSHAR(uint8_t* shar);
1244 
1251 void getSHAR(uint8_t* shar);
1252 
1259 void setSIPR(uint8_t* sipr);
1260 
1267 void getSIPR(uint8_t* sipr);
1268 
1275 void setINTLEVEL(uint16_t intlevel);
1276 
1283 uint16_t getINTLEVEL(void);
1284 
1291 void setIR(uint8_t ir);
1292 
1299 uint8_t getIR(void);
1300 
1307 void setIMR(uint8_t imr);
1308 
1315 uint8_t getIMR(void);
1316 
1323 void setSIR(uint8_t sir);
1324 
1331 uint8_t getSIR(void);
1332 
1339 void setSIMR(uint8_t simr);
1340 
1347 uint8_t getSIMR(void);
1348 
1355 void setRTR(uint16_t rtr);
1356 
1363 uint16_t getRTR(void);
1364 
1371 void setRCR(uint8_t rcr);
1372 
1379 uint8_t getRCR(void);
1380 
1387 void setPTIMER(uint8_t ptimer);
1388 
1395 uint8_t getPTIMER(void);
1396 
1403 void setPMAGIC(uint8_t pmagic);
1404 
1411 uint8_t getPMAGIC(void);
1412 
1419 void setPHAR(uint8_t* phar);
1420 
1427 void getPHAR(uint8_t* phar);
1428 
1435 void setPSID(uint16_t psid);
1436 
1443 uint16_t getPSID(void);
1444 
1451 void setPMRU(uint16_t pmru);
1452 
1459 uint16_t getPMRU(void);
1460 
1466 void getUIPR(uint8_t* uipr);
1467 
1473 uint16_t getUPORTR(void);
1474 
1481 void setPHYCFGR(uint8_t phycfgr);
1482 
1489 uint8_t getPHYCFGR(void);
1490 
1496 uint8_t getVERSIONR(void);
1497 
1499 
1501 // Socket N register I/O function //
1503 
1510 void setSn_MR(uint8_t sn, uint8_t mr);
1511 
1518 uint8_t getSn_MR(uint8_t sn);
1519 
1527 void setSn_CR(uint8_t sn, uint8_t cr);
1528 
1535 uint8_t getSn_CR(uint8_t sn);
1536 
1544 void setSn_IR(uint8_t sn, uint8_t ir);
1545 
1552 uint8_t getSn_IR(uint8_t sn);
1553 
1561 void setSn_IMR(uint8_t sn, uint8_t imr);
1562 
1569 uint8_t getSn_IMR(uint8_t sn);
1570 
1576 uint8_t getSn_SR(uint8_t sn);
1577 
1585 void setSn_PORT(uint8_t sn, uint16_t port);
1586 
1593 uint16_t getSn_PORT(uint8_t sn);
1594 
1602 void setSn_DHAR(uint8_t sn, uint8_t* dhar);
1603 
1611 void getSn_DHAR(uint8_t sn, uint8_t* dhar);
1612 
1620 void setSn_DIPR(uint8_t sn, uint8_t* dipr);
1621 
1629 void getSn_DIPR(uint8_t sn, uint8_t* dipr);
1630 
1638 void setSn_DPORT(uint8_t sn, uint16_t dport);
1639 
1646 uint16_t getSn_DPORT(uint8_t sn);
1647 
1655 void setSn_MSSR(uint8_t sn, uint16_t mss);
1656 
1663 uint16_t getSn_MSSR(uint8_t sn);
1664 
1672 void setSn_TOS(uint8_t sn, uint8_t tos);
1673 
1680 uint8_t getSn_TOS(uint8_t sn);
1681 
1689 void setSn_TTL(uint8_t sn, uint8_t ttl);
1690 
1697 uint8_t getSn_TTL(uint8_t sn);
1698 
1706 void setSn_RXBUF_SIZE(uint8_t sn, uint8_t rxbufsize);
1707 
1714 uint8_t getSn_RXBUF_SIZE(uint8_t sn);
1715 
1723 void setSn_TXBUF_SIZE(uint8_t sn, uint8_t txbufsize);
1724 
1731 uint8_t getSn_TXBUF_SIZE(uint8_t sn);
1732 
1738 uint16_t getSn_TX_FSR(uint8_t sn);
1739 
1745 uint16_t getSn_TX_RD(uint8_t sn);
1746 
1754 void setSn_TX_WR(uint8_t sn, uint16_t txwr);
1755 
1762 uint16_t getSn_TX_WR(uint8_t sn);
1763 
1769 uint16_t getSn_RX_RSR(uint8_t sn);
1770 
1778 void setSn_RX_RD(uint8_t sn, uint16_t rxrd);
1779 
1786 uint16_t getSn_RX_RD(uint8_t sn);
1787 
1793 uint16_t getSn_RX_WR(uint8_t sn);
1794 
1802 void setSn_FRAG(uint8_t sn, uint16_t frag);
1803 
1810 uint16_t getSn_FRAG(uint8_t sn);
1811 
1819 void setSn_KPALVTR(uint8_t sn, uint8_t kpalvt);
1820 
1827 uint8_t getSn_KPALVTR(uint8_t sn);
1828 
1830 
1832 // Sn_TXBUF & Sn_RXBUF IO function //
1834 
1837 uint16_t getSn_RxMAX(uint8_t sn);
1838 
1842 uint16_t getSn_TxMAX(uint8_t sn);
1843 
1859 void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
1860 
1876 void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
1877 
1885 void wiz_recv_ignore(uint8_t sn, uint16_t len);
1886 
1887 #endif // _W5500_H_